Library

Course materials — from the first wire to the assembler.

Contents

Level Guides — step-by-step walkthroughs of 47 tasks
Course Parts — overviews of the five parts: the arc, the main ideas, what you build
Component Guides — datasheets for all elements
Circuitry Articles — theory and concepts
Verilog / Hardware Programming — "From Code to Silicon" article series
For Teachers — methodology materials for course implementation
Course Curriculum — timeline of 67 levels: task, difficulty, time, and outcome
Circuit design: where to start — the topic hub: the field, four skills, the 47-level path and books
Intros — interactive explanations before 14 key levels: experiment, rule, transfer, why it matters

Level Guides

Step-by-step task descriptions and solutions for each of the 67 levels.

Course Parts

The 67 levels are divided into five released parts; all five parts are released — from a wire to a pipelined RISC core. Each overview explains why the part exists, which ideas it introduces and what you will have built by the end.

1–16

Part 1 · Basics

From the first wire and a NAND to the program counter: gates, adders, multiplexer, SR latch, D flip-flop, register, ALU, clock.

17–29

Part 2 · Advanced Architecture

Instruction decoder and the final Harvard processor with assembler, then peripherals: variable PC step, dual ROM read, IX pointers, buses and I/O ports, status flags, the final Snake.

30–43

Part 3 · Verilog

Hardware description language: primitives, module hierarchy, buses, ALU, RAM, datapath, multi-file projects, RTL Viewer, and waveforms.

44–47

Part 4 · Computer Design

Control unit, custom instruction set (ISA), memory-mapped I/O, and export to a real Tang Nano 9K FPGA.

48–67

Part 5 · RISC Microarchitecture

RISC Lab: a 32-bit RV32I teaching core in Verilog — register file, load/store, a single-cycle core and a five-stage pipeline with forwarding, the load bubble and flush.

Component Guides

All components with pictures — on one page →

How gates are built from NAND — circuits and transistor budget →

Basic Logic

Input — signal source, toggled by click
Output — circuit output port, verified by the test
NAND — universal logic gate, truth table
NOT (Inverter) — simplest logic gate, signal inversion
AND — logical multiplication, bit masking
OR — logical addition, combining conditions
XOR (Exclusive OR) — controlled inverter, adder foundation
NOR — RS latch foundation, universal element

Arithmetic and Routing

Half Adder — two-bit addition
Full Adder — ripple-carry chain
ADDER8 — 8-bit adder, level 8 reward
ALU8 — 8 operations: ADD, SUB, AND, OR, XOR, NOT, SHL, SHR
MUX (2→1) — multiplexer, digital switch
BusMUX — bus multiplexer, byte selection
Splitter — bus to 8 bits
Maker — 8 bits to bus
BusInput — 8-bit input, slider value 0–255
BusOutput — 8-bit output, decimal display
BusConstant — bus constant, masks and addresses
BusNOT — bitwise NOT, complement to 255
BusAND — bitwise AND, bus conflict prevention
BusOR — bitwise OR, setting bits
BusXOR — bitwise XOR, comparison and toggle
BusSHL — shift left, multiply by 2
BusSHR — shift right, divide by 2
BusZero — zero detector on bus

Memory and State

DFF (D Flip-Flop) — stores a bit on Clock edge
Register8 — 8-bit register, processor accumulator
IndexRegister (IX) — index register, indirect addressing
RAM (256 bytes) — random access memory, read/write
ROM (256 bytes) — read-only memory, program storage

Peripherals (Memory-Mapped I/O)

MatrixDisplay 16x16 — matrix display, ports 0xFC/0xFD/0xFF
Gamepad — 4-button gamepad, port 0xFE
LFSR (RNG) — random number generator, port 0xFA
LED8 — LED bar, byte visualization
Manual Clock — manual clock generator

Processor and Control

Clock — clock generator, circuit synchronization
Display — dec/bin/hex display, debugging
ProgramCounter — program counter, +Inc per clock
Decoder — instruction decoder, 9 control signals
Decoder V2 — instruction decoder V2: separate JZ/JN, accumulator WE, 12 signals
AddrDecoder — address decoder, RAM vs I/O
Assembler — architecture, instruction set, syntax, debugging
RISC Lab Assembler — 32 registers, RV32I formats, assembly errors, examples

Circuitry Articles

Verilog / Hardware Programming

"From Code to Silicon" series — learn Verilog and build your own hardware.

Silicon Instead of Code: Why Verilog Is Not Programming
Verilog for Beginners: Your First Module in 15 Minutes
How Hardware Makes Decisions (Life Without if/else)
Teaching Silicon Math (The Secret of '+')
Hierarchy: How Not to Drown in Wires
Data Buses: From Individual Bits to Bytes
ALU: The Heart of Your Processor
Verilog: Memory and Time — flip-flops, registers, RAM
Debugging Verilog Circuits — diagnostics, wire dumps, first failing tick
Tang Nano 9K: From ZIP to Board — taking the project to real hardware

Tools and sections

Online tools for practice and thematic hubs.

Logic Circuit Simulator — a free online simulator: 67 levels from a wire to a processor
Truth Table Generator — a full table for any Boolean formula
Number Base Converter — binary, decimal and hexadecimal
Boolean Function Calculator — PDNF, PCNF, the Zhegalkin polynomial, minimization and Karnaugh maps
Verilog and FPGA hub — where to start: articles, level 47 guide, Ershov Board
RISC Microarchitecture hub — the next stage, RISC Lab: methodology, 20 levels, development status
Comparison with other projects — NandGame, Turing Complete, Nand2Tetris

For Teachers

Methodology materials for integrating the Ershov Computer course into the curriculum.

Ershov and "Programming — The Second Literacy" — why the course bears this name
Methodology Guide — course philosophy, hardware platform, debugging, final project
The Competency Map — how to read the Skills tab: statuses, working with the graph, the teacher dashboard, methodological grounds
Project Pitch — pitch for school administration: value, outcomes, career guidance
What Makes the Ershov Computer Unique — competitive analysis: comparison with Nand2Tetris, Turing Complete, CircuitVerse and HDLBits
Ershov Board — Technical Specification — component base, pin mapping, silkscreen, Ershov Loader
Course Curriculum — timeline of 67 levels: task, difficulty, time, and a measurable outcome for each