Library

Level Guides

Step-by-step task descriptions and solutions for each of the 47 levels.

1. 1. Let there be light!
2. 2. Negation
3. 3. Perfect pair
4. 4. At least one
5. 5. Strict choice
6. 6. Half Adder
7. 7. Full Adder
8. 8. 8-bit Adder
9. 9. Crossroads
10. 10. Loopback
11. 11. Smart memory
12. 12. Tangible Memory
13. 13. Operation Selection
14. 14. Heart of math
15. 15. System Pulse
16. 16. Program Counter
17. 17. Anatomy of a Decoder
18. 18. FINALE: The Ershov Computer
19. 19. Step Forward (PC+2)
20. 20. Dual Read
21. 21. Pointers
22. 22. Bus Conflict
23. 23. Gamepad
24. 24. Manual Pixel
25. 25. Negative Check
26. 26. Dice Roll
27. 27. Hello, Ports!
28. 28. Moving Dot
29. 29. FINALE: Snake
30. 30. Hello, Wire!
31. 31. Flow Control (MUX)
32. 32. First Computation
33. 33. Scaling Circuits
34. 34. Transition to Data Buses
35. 35. Computation Center (ALU)
36. 36. ALU
37. 37. Memory and Time
38. 38. Step by Step
39. 39. Random Access Memory
40. 40. Heart of the CPU
41. 41. System Anatomy
42. 42. X-Ray for Silicon
43. 43. Freezing Time
44. 44. Control Unit
45. 45. My ISA
46. 46. Memory-Mapped I/O
47. 47. Create Computer

Component Guides

All components with pictures — on one page →

Basic Logic

• Input — signal source, toggled by click
• Output — circuit output port, verified by the test
• NAND — universal logic gate, truth table
• NOT (Inverter) — simplest logic gate, signal inversion
• AND — logical multiplication, bit masking
• OR — logical addition, combining conditions
• XOR (Exclusive OR) — controlled inverter, adder foundation
• NOR — RS latch foundation, universal element

Arithmetic and Routing

• Half Adder — two-bit addition
• Full Adder — ripple-carry chain
• ADDER8 — 8-bit adder, level 8 reward
• ALU8 — 8 operations: ADD, SUB, AND, OR, XOR, NOT, SHL, SHR
• MUX (2→1) — multiplexer, digital switch
• BusMUX — bus multiplexer, byte selection
• Splitter — bus to 8 bits
• Maker — 8 bits to bus
• BusInput — 8-bit input, slider value 0–255
• BusOutput — 8-bit output, decimal display
• BusConstant — bus constant, masks and addresses
• BusNOT — bitwise NOT, complement to 255
• BusAND — bitwise AND, bus conflict prevention
• BusOR — bitwise OR, setting bits
• BusXOR — bitwise XOR, comparison and toggle
• BusSHL — shift left, multiply by 2
• BusSHR — shift right, divide by 2
• BusZero — zero detector on bus

Memory and State

• DFF (D Flip-Flop) — stores a bit on Clock edge
• Register8 — 8-bit register, processor accumulator
• IndexRegister (IX) — index register, indirect addressing
• RAM (256 bytes) — random access memory, read/write
• ROM (256 bytes) — read-only memory, program storage

Peripherals (Memory-Mapped I/O)

• MatrixDisplay 16x16 — matrix display, ports 0xFC/0xFD/0xFF
• Gamepad — 4-button gamepad, port 0xFE
• LFSR (RNG) — random number generator, port 0xFA
• LED8 — LED bar, byte visualization
• Manual Clock — manual clock generator

Processor and Control

• Clock — clock generator, circuit synchronization
• Display — dec/bin/hex display, debugging
• ProgramCounter — program counter, +Inc per clock
• Decoder — instruction decoder, 9 control signals
• Decoder V2 — instruction decoder V2: separate JZ/JN, accumulator WE, 12 signals
• AddrDecoder — address decoder, RAM vs I/O
• Assembler — architecture, instruction set, syntax, debugging

Circuitry Articles

• Introduction to Circuitry
• How a Computer Works: A Guide for Students and Parents
• How a Processor Works: From Transistor to Program
• From Transistor to Logic Gate — where logic is born
• The Hexadecimal Number System
• Two's Complement: Negative Numbers
• How Computers Store Text: ASCII and UTF-8
• Bitwise Operations and Masks
• Timing Diagram: How to Read Circuit Behavior
• Propagation Delay: Why Signals Arrive Late
• Zhegalkin Polynomial: Any Boolean Function as One Formula
• Learn Assembly from Scratch: 15 Instructions and a Training Emulator
• The Art of Electronics: Horowitz and Hill — what is inside and how to read it
• Circuitry Books: Five Textbooks on Logic and Digital Design
• Schematics Engineer: What the Job Is and How to Get Into It
• RISC-V Architecture: An Open Processor Standard in Plain Language
• How Many Transistors Are in a Processor: From 2,300 to 20 Billion
• How to Read a Schematic: Symbols, Nets, and Common Mistakes
• Combinational vs Sequential Logic: What Is the Difference
• Logic Levels: TTL and CMOS, Why 5 V and 3.3 V Cannot Be Connected Directly
• Setup and Hold: Why Metastability Cannot Be Fixed
• FPGA, ASIC or Microcontroller: How to Choose for the Job

Verilog / Hardware Programming

"From Code to Silicon" series — learn Verilog and build your own hardware.

• Silicon Instead of Code: Why Verilog Is Not Programming
• Verilog for Beginners: Your First Module in 15 Minutes
• How Hardware Makes Decisions (Life Without if/else)
• Teaching Silicon Math (The Secret of '+')
• Hierarchy: How Not to Drown in Wires
• Data Buses: From Individual Bits to Bytes
• ALU: The Heart of Your Processor
• Verilog: Memory and Time — flip-flops, registers, RAM
• Tang Nano 9K: From ZIP to Board — taking the project to real hardware

Tools and sections

Online tools for practice and thematic hubs.

• Logic Circuit Simulator — a free online simulator: 47 levels from a wire to a processor
• Truth Table Generator — a full table for any Boolean formula
• Number Base Converter — binary, decimal and hexadecimal
• Boolean Function Calculator — PDNF, PCNF, the Zhegalkin polynomial, minimization and Karnaugh maps
• Verilog and FPGA hub — where to start: articles, level 47 guide, Ershov Board
• Comparison with other projects — NandGame, Turing Complete, Nand2Tetris

For Teachers

Methodology materials for integrating the Ershov Computer course into the curriculum.

• Ershov and "Programming — The Second Literacy" — why the course bears this name
• Methodology Guide — course philosophy, hardware platform, debugging, final project
• Project Pitch — pitch for school administration: value, outcomes, career guidance
• Ershov Board — Technical Specification — component base, pin mapping, silkscreen, Ershov Loader
• Course Curriculum — timeline of 47 levels: task, difficulty, time, and a measurable outcome for each