Level 33: HalfAdder (Verilog)

Task

Write a half adder in Verilog. A half adder adds two bits and produces two outputs: sum and carry.

Module HalfAdder has two 1-bit inputs (a, b) and two outputs (sum, carry).

Solution

A half adder has two independent logic functions on the same inputs: sum = a XOR b, carry = a AND b. Both compute in parallel — Verilog lines describe simultaneous connections.

1. Sum: xor g1(sum, a, b);
2. Carry: and g2(carry, a, b);

No internal wires needed — gate outputs connect directly to the module ports. Both XOR and AND read the same a and b inputs simultaneously. Each instance needs a unique name (g1, g2).