The Competency Map: What the Skills Tab Shows
My Computer (the game menu item) opens five tabs: Levels, Plan, Computer map, RISC core build map, and Skills. The last one shows the course not as a list of levels but as a set of abilities: 17 competencies on a graph with prerequisites. This article explains where the statuses come from, how students and teachers can work with the map, and which methodological principles it is built on.
Three chains instead of a level list
Competencies are grouped into three column-chains:
| Chain | What it builds | Route |
|---|---|---|
| Logic & arithmetic | From NAND to the ALU and structural Verilog | NAND → Boolean composition → adder & carry → multiplexer → ALU → structural Verilog |
| Memory & CPU | From the latch to FPGA and pipeline | Feedback & latch → clock & flip-flop → register & counter → CPU → bus & memory → FPGA & pipeline |
| Observation & verification | Engineering habits of debugging | Dynamic observation → crash test → fault localization → timing diagram → scenario verification |
Arrows between nodes are prerequisites: "Adder & carry" rests on NAND and Boolean composition. Five nodes carry a diamond ◆ — these are the anchor competencies: NAND as a universal basis, the ALU, clock & flip-flop, the CPU, and scenario verification. The course tests them more than once: the same abilities are checked on levels from different parts, from schematics to Verilog and RISC.
A competency is not a level
A completed level answers "what did you do here". A competency answers "what can you do now, and where was it checked". A level's wording sounds like a task: "build AND from NAND + NOT". A competency's wording sounds like an ability: "builds any basic logic operation from a single universal element and justifies the universality of the basis".
That is why one competency is linked to several levels, with different roles:
- intro — the level where the ability is introduced;
- practice — consolidation levels;
- anchor — levels where the ability is tested in a new setting (for example, the same ability is reinforced on levels 36 and 45, this time in Verilog);
- reuse — levels that use the ability but do not change the status.
The status of a competency is derived from your regular progress: level completions, concept-check answers, and the hint history in your profile. There are no separate "exams" to take.
Five statuses and the placement badge
Every node on the graph is colored with one of five statuses:
| Status | What it means |
|---|---|
| Not started | None of the formation levels are done. |
| Emerging | Some formation levels are done. |
| Built ✓ | All formation levels are done: the circuit was assembled with your own hands. |
| Verified | Built, and you correctly explained how it works in the concept checks. Without those answers the status stays at "Built": it is the ceiling for building without explaining. |
| Independent | Verified, and the checks were passed on the first attempt with no hints spent on the formation levels. |
A separate badge, Д ("from placement"), means the topic was confirmed by the placement test: the student arrived already knowing it. The badge does not change the node status; it only hints that part of the material is familiar, and the level checks still have to be passed. The other side matters too: statuses are computed only from current data. If hints were spent before statistics started being collected, the maximum stays at "Verified": the map does not fill in missing data.
How to work with the map
Clicking a node opens a card: the full ability, the status, the counter "formation levels: 2 of 3 done", level chips (a jump straight to a level), and the prerequisites with their statuses. If a prerequisite is not built, you can see what to strengthen before returning to the node.
The selected node highlights the path: the prerequisite edges leading to it get a running dash, and you can see which abilities the road to the goal runs through.
"Path to this level" in a task. On most levels the task panel shows the abilities of this level and the chain of their nearest prerequisites with their statuses. It is the same graph shown locally: level 41 appears as a step in the CPU ability, which rests on the register, the ALU and the multiplexer.
For a student, the map answers three questions: what already works, what is missing, and which level unlocks the next node. If "Built" refuses to become "Verified", return to the formation levels: after a level is passed again, its concept check reappears, and the "why this works" question can be answered correctly. Such answers are what move the status forward.
The map in the teacher dashboard
In the teacher dashboard, under Analytics, the Course Programme sub-tab shows the same map as two tables: the "competencies × levels" registry with roles and evidence types, and a "student × competencies" matrix with each student's statuses. Statuses are computed from the progress snapshots the account client sends to the server (the same mechanism as in the game, across the class).
The matrix gives a picture of the class: you can see where the group moves evenly and where it hits a wall — for example, the whole class stuck at "Emerging" on Clock & flip-flop. The printable department report includes a competency status summary. A practical routine: after a lesson, open the matrix and pick the next level by the weakest node that has formation levels ready.
Methodological grounds
The map rests on several well-established didactic constructs.
A competency instead of a topic list. The split between "the level's task" and "a transferable ability" follows the approach of evidence-centered design: Mislevy, Almond and Lukas formalized assessment as a chain "what the student does → what evidence it provides → what conclusion about the ability" (Mislevy R. J., Almond R. G., Lukas J. F., "A Brief Introduction to Evidence-Centered Design", ETS Research Report RR-03-16, 2003). The course levels are evidence tasks; the node status is a conclusion drawn over several pieces of evidence. That is also where the level roles come from: intro, practice and anchor are different types of evidence about the same ability.
A ladder of depth. Assembling a circuit is application (apply) in the terms of the revised Bloom taxonomy; explaining and predicting require comprehension and analysis (understand, analyze; Anderson L. W., Krathwohl D. R., "A Taxonomy for Learning, Teaching, and Assessing", 2001). Webb's Depth-of-Knowledge scale distinguishes reproducing a procedure from applying a concept in an unfamiliar setting (Webb N. L., "Depth-of-Knowledge Levels", 2002). That is why "Built" and "Verified" are two different statuses.
Mastery before moving on. Prerequisites on the graph implement the mastery learning model: Bloom showed that when each block is checked for mastery before the next, a group reaches markedly better results than under calendar-driven pacing (Bloom B. S., "Learning for Mastery", 1968). Prerequisite edges and the "which level unlocks the next node" hint put the same logic into the interface: the next block makes sense once the current one is built.
Formative assessment. Statuses update from ordinary work (checks, quizzes, hints) and are visible to the student immediately. This is formative assessment in Black and Wiliam's sense: assessment serving as feedback inside learning (Black P., Wiliam D., "Inside the Black Box: Raising Standards Through Classroom Assessment", Assessment in Education, 1998). Showing the "Independent" status also serves a motivational purpose: careful work without hints leaves a visible trace.
There are deliberate limitations. Thresholds for the higher statuses are being calibrated with pilot data; the placement badge intentionally does not count as a check; some abilities (for example, designing a verification scenario on your own) are assessed only at the anchor levels where such scenarios are actually built. The map is a navigator, not a transcript: the final picture of a student's abilities comes from the map together with the part certificates and the engineer profile.