Course Curriculum

All 47 levels, from the first wire to an FPGA: for each — the task, difficulty, typical time, and a measurable learning outcome.

1–16 ≈ 330 min · ≈ 5.5 h

Part 1 · Basics

From the first wire and a NAND to the program counter: gates, adders, multiplexer, SR latch, D flip-flop, register, ALU, clock.

17–29 ≈ 415 min · ≈ 6.9 h

Part 2 · Advanced Architecture

Instruction decoder and the final Harvard processor with assembler, then peripherals: variable PC step, dual ROM read, IX pointers, buses and I/O ports, status flags, the final Snake.

30–43 ≈ 360 min · ≈ 6 h

Part 3 · Verilog

Hardware description language: primitives, module hierarchy, buses, ALU, RAM, datapath, multi-file projects, RTL Viewer, and waveforms.

44–47 ≈ 135 min · ≈ 2.3 h

Part 4 · Computer Design

Control unit, custom instruction set (ISA), memory-mapped I/O, and export to a real Tang Nano 9K FPGA.

47 ≈ 1240 min

Total: ≈ 21 h of pure solving

≈ 28 lessons of 45 minutes of pure solving; with theory, articles, and review — ≈ 40 lessons (30 h).

School implementation formats

Year-long elective

2 lessons a week (45 min each) — all 47 levels fit into one school year.

Half-year club

4 lessons a week — the full course fits into one semester.

Intensive

5 days × 6 hours — a summer school or profile camp format.

Lesson-by-lesson plan

The plan targets the year-long format of two lessons a week: 39 lessons. A regular lesson runs up to 45 minutes; the two finale lessons (parts 2 and 3) take 60. Pure level solving takes ≈28 lessons; the rest is theory, articles, and review. Each level number links to its guide.

LessonLevels≈minTopicTheory and reviewHomework
1 1, 2 15 Signal and negation Review: a signal as 0/1 and NAND as a universal gate; after level 2, the concept check on building NOT from NAND. Read the article on AND, OR, NOT gates.
2 3, 4 25 AND, OR and De Morgan Review the De Morgan article: how to build a missing gate from the ones you have. Write out AND and OR truth tables on paper for all input combinations.
3 5, 6 30 Selection and the first adder Review: how "all inputs" differs from "at least one", and why adding two bits produces two outputs. Read the adder anatomy article.
4 7, 8 45 Carry and 8-bit addition Review the adder anatomy article: the carry chain from bit to bit. Add three pairs of 8-bit numbers by hand and write down the carries.
5 9 20 The switch: multiplexer Review the multiplexer article: a control wire picks the signal route. Come up with two places in a computer that need to pick one of several signals.
6 10 25 Feedback: the SR latch Review the feedback article: why a circuit with a loop remembers. Read the SR latch article and sketch its two stable states.
7 11 30 D flip-flop Review the clock and D flip-flop article: writing on the clock edge. Read the clock and D flip-flop article.
8 12 30 Register: the first byte of memory Review the registers article: eight D flip-flops acting as one cell. Explain out loud how a register differs from a single flip-flop.
9 13 30 Operation select: the ALU scheme Review the ALU article: the decoder picks the operation, the multiplexer picks the result. Read the ALU article.
10 14 40 The Zero flag and comparison Review: how subtraction and the zero flag turn a circuit into a device that can compare. Think about which numbers do not fit into the unsigned 8-bit range.
11 15, 16 40 The clock and the program counter Review the program counter article: PC plus clock makes a machine that steps through a program. Read the program counter article.
12 17 30 The instruction decoder Review the instruction decoder article: opcode bits become control signals. Write down all 4 opcodes and their control signals.
13 18 60 FINALE: the full Harvard processor Review the Harvard architecture article: why ROM and RAM are separate and how the instruction cycle runs. Sketch the processor datapath from memory and check it against the game.
14 19, 20 35 Variable PC step Review the level 19 concept check: the PC step equals the instruction size. Re-read the program counter article, now with the +2 step.
15 21 25 The IX pointer Review the pointers and index registers article: an address used as data. Think of a task that is impossible without a pointer.
16 22 30 The bus and device conflicts Review the bus conflicts and address decoder article: everyone stays quiet while one device talks. Read the bus conflicts article.
17 23 30 Assembler and port 254 Review the assembly article and the LDA/ADD difference using the gamepad port. Read the assembly article.
18 24 25 A pixel on screen Review: writing a byte to the display address — the first picture drawn by a program. Draw a cross on the display with a three-line program.
19 25 30 Flags and two's complement Review the two's complement article: number sign and CPU flags. Read the two's complement article.
20 26 20 Pseudo-random numbers Review: where "randomness" comes from in a deterministic circuit. Think of how to get a "random" move from a player's keypress.
21 27 25 I/O ports Review the memory-mapped I/O article: the address space as the interface to everything. Read the memory-mapped I/O article.
22 28 45 Branching and movement Review the branching and loops article and the concept check: JZ is physically a MUX before the PC. Read the branching and loops article.
23 29 60 FINALE: Snake Review the finished Snake program: RAM as variables, an empty loop as the timer. —
24 30, 31 25 Hello, Verilog and strict choice (XOR) Review the Verilog for beginners article: a module, its ports, the first textual circuit. Read the "Verilog is not programming" article.
25 32, 33 30 Flow control and first computation Review: a multiplexer in Verilog and a half adder (XOR + AND). Read the Verilog half adder article.
26 34 20 Module hierarchy: FullAdder Review the Verilog hierarchy article: a full adder from two half adders. Read the module hierarchy article.
27 35 30 Buses and the 8-bit adder Review the Verilog buses article: a vector instead of eight wires, and Adder8 from FullAdder. Read the Verilog buses article.
28 36 40 The full ALU Review: how the familiar circuit of level 14 becomes text and passes the same tests. Compare the level 14 schematic with the level 36 text line by line.
29 37 30 Memory and the clock Review the concept check: the clock is for storing, not for computing. Re-read the clock and D flip-flop article in the Verilog context.
30 38 25 A counter step by step Review: register plus adder plus feedback equals a counter; debugging tick by tick. Read the sequential circuits section of the level guide.
31 39 30 RAM as a black box Review the Verilog hierarchy article: the interface matters more than the insides. Read the module hierarchy article.
32 40 40 The processor datapath Review: rebuild the whole datapath as text, from registers to the ALU. Compare the textual datapath with the level 18 schematic.
33 41 35 Hierarchy: a CPU from modules Review the Verilog hierarchy article and multi-file projects: instantiation embeds a circuit. Split your project into one file per module.
34 42 20 RTL Viewer: an X-ray of the circuit Review: what the synthesizer grew from your text and how to read its schematic. Open the RTL Viewer for level 40 and find your modules in it.
35 43 35 Delays and waveforms Review the propagation delay article and reading a waveform at the clock edge. Read the propagation delay article.
36 44 25 The control unit Review the instruction decoder article: the CU is a big decoder without memory. Write down the opcodes and control signals of your circuit.
37 45 35 A custom instruction Review the crash test: the decoder defines what a command means, not the gates. Think of an instruction missing from the instruction set.
38 46 30 Memory-Mapped I/O Review the memory-mapped I/O article: address 0xFF as a door to the real world. Read the memory-mapped I/O article.
39 47 45 Materialization: from Verilog to the board Review the Ershov Board spec article: synthesis into LUTs and flip-flops, routing, flashing the Tang Nano 9K. —

Part 1 · Basics · Levels 1–16 · ≈ 330 min

1

Let there be light!

Task: Connect the signal source (Input) to the receiver (Output).

●○○ ≈ 5 min
After the level: explain what a 0/1 signal, an input/output pin, and a wire are, and connect a source to a receiver
Guide Open level →
2

Negation

Task: Build a NOT gate from a NAND. When the input is 1, the output should be 0.

●○○ ≈ 10 min
After the level: explain why a NAND with tied inputs turns into a NOT (functional completeness)
Guide Open level →
3

Perfect pair

Task: Build a logical AND gate.

●○○ ≈ 10 min
After the level: build an AND from NAND + NOT and explain operation composition
Guide Open level →
4

At least one

Task: Build a logical OR gate.

●○○ ≈ 15 min
After the level: build an OR using De Morgan's law and explain the formula NOT(NOT A AND NOT B)
Guide Open level →
5

Strict choice

Task: Build an Exclusive OR (XOR) gate.

●○○ ≈ 15 min
After the level: build an XOR from basic gates and explain it as a "controlled inverter"
Guide Open level →
6

Half Adder

Task: Build a Half Adder.

●●○ ≈ 15 min
After the level: explain how adding two bits yields two outputs (Sum, Carry) and build a half adder
Guide Open level →
7

Full Adder

Task: Build a Full Adder: 3 inputs, 2 outputs.

●●○ ≈ 20 min
After the level: explain carry propagation between bits and build a full adder
Guide Open level →
8

8-bit Adder

Task: Build an 8-bit adder (ADDER8) using FullAdders and buses.

●●○ ≈ 25 min
After the level: explain what a bus and a byte are, and build an 8-bit adder as a chain of carries
Guide Open level →
9

Crossroads

Task: Build a multiplexer (MUX): selects one of two input bits.

●●○ ≈ 20 min
After the level: explain how a multiplexer works as a "digital switch" and its selection formula
Guide Open level →
10

Loopback

Task: Build an SR latch from NOR gates. State is held when S=0, R=0.

●●○ ≈ 25 min
After the level: explain what feedback is and how two NOR gates form an SR latch (the first memory)
Guide Open level →
11

Smart memory

Task: Build a D flip-flop (DFF). Data is captured on the rising edge of the Clock.

●●○ ≈ 30 min
After the level: explain the role of the clock edge and how a master-slave D flip-flop works
Guide Open level →
12

Tangible Memory

Task: Build an 8-bit register from DFFs. Connect its output to LED8.

●●● ≈ 30 min
After the level: explain how 8 flip-flops form a byte-wide register (parallel cells)
Guide Open level →
13

Operation Selection

Task: Build an operation selector. BusMUX picks the result: ADD, AND, or OR based on OpSelect.

●●● ≈ 30 min
After the level: explain how a cascade of multiplexers routes the result of the required operation
Guide Open level →
14

Heart of math

Task: Build an 8-bit ALU (ADD, AND, OR, XOR, NOT, SHL, SHR). Hint: decoder -> operations -> MUX.

●●● ≈ 40 min
After the level: explain the ALU architecture (decoder → operations → MUX) and the purpose of the Zero flag
Guide Open level →
15

System Pulse

Task: Learn the concept of clocking. Press ManualClock and watch the counter on the LED8.

●●● ≈ 10 min
After the level: explain how a clock moves data through registers and manually clock a counter
Guide Open level →
16

Program Counter

Task: Build a Program Counter (PC) from a Register and ADDER8. Each clock tick increments the address by 1.

●●● ≈ 30 min
After the level: build a program counter and explain the register → ALU → register cycle
Guide Open level →

Part 2 · Advanced Architecture · Levels 17–29 · ≈ 415 min

17

Anatomy of a Decoder

Task: Build the recognition logic for 3 opcodes (ADD, STA, JMP) in the decoder. LED indicators on the outputs show which line is active.

●●● ≈ 30 min
After the level: explain how an opcode is recognized by chains of ANDs (decoder)
Guide Open level →
18

FINALE: The Ershov Computer

Task: Build an 8-bit computer! Harvard architecture: ROM (instructions) + RAM (data) + PC + Register + ALU + Decoder + Clock.

●●● ≈ 60 min
After the level: explain the instruction fetch-execute cycle and the Harvard architecture (ROM + RAM)
Guide Open level →
19

Step Forward (PC+2)

Task: Connect BusConstant(2) to the PC Inc input so the PC steps by +2 instead of +1.

●●○ ≈ 15 min
After the level: explain why the program counter needs a variable step (word-format instructions)
Guide Open level →
20

Dual Read

Task: Add a second ROM for reading 2-byte operands. PC steps by +2.

●●○ ≈ 20 min
After the level: explain how a single PC addresses two ROM banks (dual read)
Guide Open level →
21

Pointers

Task: Add Index Register (IX) for indirect addressing. Implement LDX, LDAX, STAX, INX in the decoder.

●●● ≈ 25 min
After the level: explain pointers and indirect addressing at the level of the IX register
Guide Open level →
22

Bus Conflict

Task: Fix the data bus conflict: RAM and Gamepad both drive the bus. Add AddrDecoder and BusAND to gate the RAM output.

●●● ≈ 30 min
After the level: explain a bus conflict and how an address decoder separates devices (gating)
Guide Open level →
23

Gamepad

Task: Write a program that reads the gamepad (port 254) and stores the value in RAM[0].

●●● ≈ 30 min
After the level: write a program that reads an input port and explain the difference between LDA N and ADD N
Guide Open level →
24

Manual Pixel

Task: Connect 4 BusConstants to the MatrixDisplay and light up pixel at (0,0).

●●○ ≈ 25 min
After the level: explain the memory-mapped display port protocol (X, Y, pixel) and light up a pixel
Guide Open level →
25

Negative Check

Task: Learn the JN (Jump if Negative) conditional jump. Run the test program and verify the jump works.

●●● ≈ 30 min
After the level: explain status flags (two's complement) and write a program with a conditional JN jump
Guide Open level →
26

Dice Roll

Task: Connect the LFSR (random number generator) to the data bus via a second BusOR.

●●○ ≈ 20 min
After the level: explain how an LFSR generates pseudorandom numbers and how a third source reaches the bus
Guide Open level →
27

Hello, Ports!

Task: Change the constants in the program so the pixel lights up at X=4, Y=12.

●●○ ≈ 25 min
After the level: read and modify a ready-made assembly program to meet a new condition
Guide Open level →
28

Moving Dot

Task: Write a program that moves a dot on the screen using the gamepad.

●●● ≈ 45 min
After the level: write a complete program with RAM variables, input, branching, and a loop
Guide Open level →
29

FINALE: Snake

Task: Write a complete Snake game in assembly!

●●● ≈ 60 min
After the level: design the game "Snake" in assembly: state, input, rendering
Guide Open level →

Part 3 · Verilog · Levels 30–43 · ≈ 360 min

30

Hello, Wire!

Task: Code is not an algorithm — it is a circuit blueprint. Call the basic AND gate to route your first wires in silicon. Write: and gate1(out, a, b);

●○○ ≈ 10 min
After the level: explain that Verilog describes a circuit, not an algorithm, and instantiate a gate
Guide Open level →
31

Strict Choice in Code (XOR)

Task: Build an XOR gate using only and, or, and not. The built-in xor is disabled. Key rule: lines of code here work simultaneously, like connected conductors, not sequentially.

●○○ ≈ 15 min
After the level: explain Verilog statement parallelism and build an XOR from and/or/not without the xor primitive
Guide Open level →
32

Flow Control (MUX)

Task: Design a 2→1 multiplexer. If sel=0, out=a; if sel=1, out=b.

●○○ ≈ 15 min
After the level: translate a circuit problem (MUX) into structural Verilog
Guide Open level →
33

First Computation (HalfAdder)

Task: Design a half adder. sum = a XOR b, carry = a AND b.

●○○ ≈ 15 min
After the level: build a half adder in Verilog (XOR + AND)
Guide Open level →
34

Module Hierarchy (FullAdder)

Task: Design a full adder. sum = a XOR b XOR c_in, c_out = (a AND b) OR (a AND c_in) OR (b AND c_in). You may use HalfAdder from the previous level.

●●○ ≈ 20 min
After the level: explain module hierarchy and reuse your own HalfAdder
Guide Open level →
35

Data Buses (Adder8)

Task: Design an 8-bit adder. Use 8 full adders (FullAdder) in a ripple-carry chain.

●●● ≈ 30 min
After the level: build an 8-bit adder by instantiating 8 FullAdders
Guide Open level →
36

ALU

Task: Build an 8-bit ALU. op_code=0: add (Adder8), op_code=1: bitwise AND. Use Adder8 and Mux modules from previous levels.

●●● ≈ 40 min
After the level: explain how the code structure maps to the architecture (8×and, 8×Mux)
Guide Open level →
37

Memory and Time

Task: Design an 8-bit register from D flip-flops using generate-for. module Reg8(input wire [7:0] in, input wire clk, output wire [7:0] out);

●●○ ≈ 30 min
After the level: explain sequential logic in Verilog (dff, clockPort) and generate-for
Guide Open level →
38

Step by Step

Task: Design an 8-bit counter: register + adder in feedback. Constant 8'b00000001 = +1.

●●○ ≈ 25 min
After the level: build a feedback counter broken by D flip-flops; use 8'b constants
Guide Open level →
39

Random Access Memory

Task: Wrap the built-in RAM256 for reading and writing data by address. RAM256 ports: (clk, we, addr, data, q).

●●● ≈ 30 min
After the level: wire the built-in RAM256 and explain the black-box abstraction
Guide Open level →
40

Heart of the CPU

Task: Design the datapath: Counter → ROM → ALU → Register. ROM data: 0→5, 1→7, 2→3, 3→10, 4→2. ALU adds.

●●● ≈ 40 min
After the level: build a datapath (Counter → ROM → ALU → Register) and explain the data path
Guide Open level →
41

System Anatomy

Task: Build the top-level CPU module. Instantiate Reg8 and FullAdder from neighboring files (register.v, full_adder.v) and connect them.

●●● ≈ 35 min
After the level: explain a multi-file project (VFS) and the roles of read-only library files
Guide Open level →
42

X-Ray for Silicon

Task: Explore the hierarchy through the RTL Viewer (X-ray machine for chips), find the wrong gate at the lowest level, and answer the question.

●●○ ≈ 20 min
After the level: debug hierarchy with RTL Viewer drill-down and find a misconnected primitive
Guide Open level →
43

Freezing Time

Task: Find and fix the bug in FullAdder. The test fails — open the waveform scope and find the wrong carry wire.

●●● ≈ 35 min
After the level: read a timing diagram and find and fix an error in the circuit
Guide Open level →

Part 4 · Computer Design · Levels 44–47 · ≈ 135 min

44

Control Unit

Task: Implement the instruction decoder. Input: 4-bit opcode, outputs: control signals (RegWrite, MemWrite, ALUSel, Branch). Use AND/OR/NOT gates.

●●○ ≈ 25 min
After the level: design a control unit: opcode decoder → control signals
Guide Open level →
45

My ISA

Task: Build an 8-bit ALU. Support three operations: ADD (sel=0), AND (sel=1), OR (sel=2). Use Adder8 for addition, gates for bitwise AND/OR, and a sel decoder with MUX to select the result. Use generate-for loops.

●●● ≈ 35 min
After the level: design an ALU operation selector: a 2-bit code decoder and a MUX choose one of three operations
Guide Open level →
46

Memory-Mapped I/O

Task: Implement an I/O controller. Writing to address 0xFF updates LEDs (led_out), reading 0xFE returns switch states (switches_in).

●●● ≈ 30 min
After the level: explain memory-mapped I/O and implement LED/switches with a write-enable register
Guide Open level →
47

Create Computer

Task: Write top.v, instantiate the CPU, and wire the ports. Press "Build Computer" to export the project to Tang Nano 9K.

●●● ≈ 45 min
After the level: instantiate a complete computer and export it to a real FPGA (ZIP, pin mapping)
Guide Open level →

Related reading

Part 1 · Basics

Part 2 · Advanced Architecture

Part 3 · Verilog

Project Pitch for schools → · Methodology Guide →