Level 42: Through the Silicon (Verilog)

Task

You are looking at a two-level hierarchy: the CPU module instantiates 8 FullAdder modules. All files are read-only — you cannot modify the code. Your task: explore the circuit through the RTL Viewer.

Double-click a submodule block in the RTL viewer to "drill down" inside and see its internal structure. Use the breadcrumbs to navigate back. Find the incorrectly connected primitive and answer the question.

Hint: look at the gate forming signal w3 inside FullAdder.

Solution

In file fulladder.v, gate g4 uses the primitive nand instead of and:

nand g4(w3, w1, c_in);  // bug — should be and

The signal w3 = w1 AND c_in is needed for correct carry generation: c_out = w2 OR w3, where w2 = a AND b. Using nand inverts the result, breaking the carry logic.

Answer: nand.