Level 40: Datapath (Verilog)

Task

Build a datapath — a pipeline of four components: address counter, instruction ROM, ALU, and accumulator. This is a simplified CPU model that reads commands from ROM and accumulates a result.

Module Datapath takes clk and outputs result[7:0]. ROM contains data: address 0→5, 1→7, 2→3, 3→10, 4→2. ALU performs addition (op_code = 0).

Use modules: Counter8 (level 38), ROM (builtin), ALU8 (level 36), Reg8 (level 37).

Solution

The datapath is a chain of four blocks connected sequentially, with feedback through the accumulator:

1. Declare wires: wire [7:0] addr, rom_data, alu_out; and wire carry_unused;
2. Counter generates an address: Counter8 pc(addr);
3. ROM reads data at that address: ROM rom(addr, rom_data);
4. ALU adds ROM data to current result: ALU8 alu(alu_out, carry_unused, rom_data, result, 1'b0); — op_code=0 (add)
5. Accumulator register stores the result: Reg8 acc(result, alu_out);

result is simultaneously the module output port, the accumulator output, and the b input of ALU. The feedback allows accumulating: 0 → 5 → 12 → 15 → 25 → 27.

ALU8 port order: (out, carry_out, a, b, op_code). ROM port order: (addr, data).