Logic Levels: TTL and CMOS, Why 5 V and 3.3 V Cannot Be Connected Directly

A logic zero and a logic one are not numbers, they are ranges of voltage. Inside a range the circuit does not care whether the wire sits at 0.9 V or 1.4 V: for it, that is a zero. This is exactly why two chips that both work perfectly on their own can refuse to work together when their levels do not match. The topic sounds narrow, but it is the first thing to check when "the circuit does not start even though every gate is in place". The rest of the field is collected on the Circuit Design page.

A one and a zero are ranges

Every chip has four numbers that describe its levels. Two belong to the input: VIH, the voltage from which the input must understand a one, and VIL, the voltage up to which the input must understand a zero. Two belong to the output: VOH, the lowest voltage the output produces when producing a one, and VOL, the highest voltage it produces when producing a zero. Between VIH and VIL lies a range where the input promises nothing: the value has no meaning there, and the datasheet calls it undefined.

The output numbers depend on load, temperature and supply, which is why datasheets state the conditions: "at a load current of 4 mA and a supply of 4.5 V". That yields a rule worth learning before anything else: exact numbers come from the datasheet of the exact part, not from memory. Below are typical values for a discussion of two classic families at a 5 V supply.

One look at the table explains half of an engineer's habits. A CMOS output is pulled up to its own supply almost all the way, so its one is almost Vcc, and an interface with anything whose one-threshold is lower gets a large margin. A TTL output works on current: it cannot be guaranteed to rise above roughly 2.4 V, and that is its weak side.

Noise margin: how many volts you are allowed to lose

The noise margin answers the question "how many volts can the signal lose or gain on the way and still be recognised". It is computed simply: for the high level, VOH(min) − VIH(min), for the low level, VIL(max) − VOL(max). It is the difference between the sender's worst promise and the receiver's minimum requirement.

Let's compute it for two rows of the table. For 74HC at 4.5 V: 4.4 − 3.15 = 1.25 V on the high level and 1.35 − 0.1 = 1.25 V on the low level. For classic TTL: 2.4 − 2.0 = 0.4 V and 0.8 − 0.4 = 0.4 V. This is why TTL boards had to be kept short: half a volt of margin is eaten by interference from a neighbouring signal, and on a two-metre cable also by the drop across the wire resistance. The move to CMOS essentially consisted of the noise margin growing threefold, which allowed higher frequencies and longer lines.

A related habit is worth knowing when reading a schematic: if a resistor sits on an input, it is often a pull-up. It is there not for looks but to give the input a state when the signal is disconnected. More on this in how to read a schematic, where a floating input is treated as a separate case.

Why 5 V and 3.3 V are not connected directly

Now the interfaces can be checked. The first pair is a TTL output driving a CMOS input on the same 5 V supply. A TTL output guarantees at least 2.4 V for a one, and a 74HC input is required to recognise a one from 3.15 V. Between 2.4 V and 3.15 V there is a range where both sides are right according to their datasheets, and the circuit works by accident: fine on the bench, unreliable in production. Such an interface is called incompatible, and it is not used.

The second pair is a CMOS output driving a TTL input at 5 V. Here everything lines up: VOL for CMOS is about 0.1 V, well below VIL for TTL at 0.8 V, and a one at 4.4 V covers the 2.0 V requirement with a large margin. This interface works, and it is why the move to CMOS was gradual: old boards were adapted rather than thrown away.

The third pair is the cause of most damage today: a 5 V output driving an input of a chip powered at 3.3 V. The problem is not logic but the voltage on the input. Such a part limits the voltage allowed on an input to its supply plus a small margin, and 5 V exceeds that limit. The outside of such an input looks perfectly normal: it does not run hot, and the circuit works right up until the input dies. This is why the interface is checked against the datasheet before the first power-up, and not on a board that has already stopped working.

There are known ways around this, and none of them requires invention. Parts whose part number marks TTL-compatible inputs accept old-family signals directly. A level shifter makes the translation explicit. The high level can be capped with a resistive divider: a series resistor and a resistor to ground are sized so that the input sees a level above the one-threshold but below the input limit. A divider slows the edges, so this is only done on slow signals. A pull-up resistor to 3.3 V is no help here: with an ordinary output that drives both a one and a zero, the output itself sets the level and a pull-up does not change that. For an open-collector output, a pull-up to 3.3 V is exactly the right answer, and the same resistor sets the rise time. One exception is worth knowing: many modern parts have 5 V tolerant inputs, and the datasheet says so directly, in which case the interface is fine without a translator. Choosing between the options is no longer about logic, but about compatibility, speed and cost.

Inputs and consumption: two different philosophies

Apart from levels, the families differ in how inputs behave without a signal. A classic TTL input is built around the emitter junction of a transistor, and if the wire is left detached, that input reads as a one. This is a well-known property, and people even designed circuits around it: any unused TTL input on a board simply acted as a logic one. A CMOS input is the gate of a field-effect transistor: it draws no current and can still accumulate charge. A dangling CMOS input can show anything, because the value depends on what is left on the gate from the previous state and on interference nearby. Unused CMOS inputs are therefore tied to a defined state rather than left floating.

Consumption is the mirror image. TTL draws current continuously, and every input adds its share even when the signal never changes. CMOS draws almost nothing at rest, and all the energy goes into switching: the higher the frequency and the larger the load capacitance, the more current flows, and lowering the voltage lowers consumption by itself, because capacitive power is proportional to the square of the voltage. That leads to a practical rule for a modern circuit: do not drop the supply voltage to save power without doing the maths, because voltage and noise margin and speed all leave with it, and the saving turns out to be smaller than expected.

The two families also differ in speed, and that is a separate topic rather than a consequence of the levels: CMOS propagation delay falls as the supply voltage drops, so the same gates at 3.3 V are usually faster than at 5 V. Speed on long lines is limited by the line itself, which is covered in the article on propagation delay.

How this looks in the simulator

The simulator in this course works with zeros and ones, not volts, and that is a deliberate simplification: there are no thresholds, no noise margin and no supply. Level compatibility cannot be checked in it, and any attempt runs into the absence of a model.

What transfers without loss is the second half of the topic. In the simulator an output is a source, and two outputs on one net conflict exactly as they do in hardware: whichever is stronger drives the line, and the rest read the wrong level. A bus with several outputs attached needs arbitration, and a multiplexer with an enable input is the model of switching a source on. There is no third state, where a source releases the line and leaves it at a pull-up voltage, so a pull-up is drawn explicitly on the schematic, while on the canvas it looks like a resistor or a separate source of a logic level.

The practical conclusion: levels are checked against the datasheet and on the schematic, and the simulator is used to check whether the logic is right. These are two different checks, and it is not worth mixing them.

Where the delays come from and how they accumulate is covered in the article on propagation delay, why two sources must not be connected is in bus conflicts and the address decoder, and why all of this is engineering work rather than assembly from ready-made blocks is in the schematics engineer.