How Hardware Makes Decisions (Life Without if/else)

In programming, nothing feels more natural than branching. if (x > 0) { doThis(); } else { doThat(); } — the processor checks a condition and jumps to exactly one path. The other path simply never executes. This mental model is so baked into our thinking that it's genuinely hard to imagine computing any other way.

But hardware is not software. In a Verilog circuit, there is no instruction pointer, no branch predictor, no program counter deciding which line to run next. All paths are live all the time. The current doesn't "choose" — it flows through every gate simultaneously, every nanosecond, and you, the designer, must build a mechanism that picks the right result after the fact.

This mechanism is called a multiplexer, or MUX for short.

Think of a MUX as a railroad switch. Two tracks (input A and input B) merge into one. A control signal — the selector — determines which track gets connected to the output. When sel = 0, the MUX connects input A to the output. When sel = 1, it connects input B. Crucially, both trains are arriving at the switch at the same time. The MUX doesn't stop one train and let the other through — it physically connects one set of rails and disconnects the other.

In Verilog, a 2-to-1 multiplexer looks like this:

module Mux(
    output out,
    input a,
    input b,
    input sel
);
    wire nsel, w1, w2;
    not g1(nsel, sel);
    and g2(w1, a, nsel);
    and g3(w2, b, sel);
    or g4(out, w1, w2);
endmodule

Let's trace the logic. When sel = 0, the NOT gate outputs nsel = 1. The first AND gate (g2) sees both a and 1 on its inputs — it becomes transparent, passing a through to w1. The second AND gate (g3) sees b and 0 — it's blocked, its output stays 0. The OR gate at the end combines them: w1 carries a, w2 is 0, so out = a. When sel = 1, the opposite happens: nsel = 0, the first AND gate is blocked, the second passes b, and out = b.

Think of the AND gates as guards with keys. Each guard stands at a door, and the key (the selector) opens exactly one door. The selector's inverted signal opens the other. Both doors are guarded simultaneously — the key just decides which guard steps aside.

This pattern — "compute everything, then pick" — is the fundamental strategy of hardware design. A CPU doesn't decide whether to add or subtract based on a condition. It builds an adder and a subtractor side by side, lets both run, and then a MUX selects the result based on the operation code. Engineers call this "speculative execution done at the hardware level," and it's been there since the 1970s.

Why build things this way? Because gates are cheap and time is expensive. Adding a few extra AND gates costs almost nothing in silicon area, but waiting for a conditional branch to resolve costs precious nanoseconds. By computing everything in parallel and using a MUX to select the answer, hardware achieves speed that software can only dream of.

In the Turing Complete game, Level 32 ("Mux in Verilog") asks you to build exactly this circuit. When you wire up those four gates, you're not writing a branch — you're building a physical decision-maker that runs at the speed of light through copper.