Level 38: Counter (Verilog)

Task

Build an 8-bit counter that increments by 1 on each clock tick. The counter uses feedback: the Reg8 output is fed back into the Adder8 input.

Module Counter8 takes clk and outputs out[7:0]. Use Reg8 (level 37) and Adder8 (level 35).

Solution

1. Declare intermediate wires: wire [7:0] sum; and wire carry_unused;
2. Adder adds current out plus constant 8'b00000001: Adder8 adder(sum, carry_unused, out, 8'b00000001);
3. Register stores the sum: Reg8 cnt(out, sum);

Adder8 port order: (sum, c_out, a, b, c_in). Leave c_in unconnected (defaults to 0). Constant 8'b00000001 is Verilog notation for the 8-bit value 1.