Combinational vs Sequential Logic: What Is the Difference

Every digital circuit belongs to one of two kinds, and the difference between them comes down to a single line: does the circuit remember its previous state? A combinational circuit forgets everything at once, a sequential one remembers until a clock arrives. On a schematic this looks like the difference between gates with no feedback and nodes with a Clock input. Below is where the boundary lies and why a processor cannot be built out of only one of the two kinds. Where this boundary sits in the wider field is shown on the Circuit Design page.

One question that settles everything

Take any circuit and ask it one question: what will the output be if the inputs return to the values they had before? If the answer is "the same as it was then", the circuit is combinational and has no memory. If the answer is "it depends on what happened in between", you are looking at a sequential circuit.

Formally, the difference looks like this. A combinational circuit is described by a function of the inputs, Y = f(X). A sequential circuit adds a state variable, Y = f(X, S), plus a separate block that updates the state. While the state does not change, a sequential circuit behaves like a combinational one, which is why every sequential circuit contains a combinational circuit inside it.

The combinational part: a truth table instead of a history

A combinational circuit is gates wired together so that no loop exists at the output. You apply values to the inputs, the gates settle one after another, the signal passes through the delay of each one, and the output reaches a new value. That value depends only on what is applied right now, and there is no history in the circuit. This is exactly why any combinational circuit can be described with a truth table and checked before a single transistor is involved. Karnaugh maps, covered in their own article, exist for precisely this purpose: they turn a table into a ready-made connection of gates.

One detail about delay matters. A combinational circuit is never instantaneous: a new result appears at the output not immediately but after the propagation delay, which adds up along the chain. While the signal is being recomputed, the output may hold an intermediate value that never appears in the truth table. A short glitch in the middle of a circuit is normal, and a checker will not see it. This is why the clock in a processor is chosen so that the whole combinational part has time to finish by the end of the cycle.

The sequential part: state that is not on the sheet

A sequential circuit adds to the logic an element that can remember one bit. In a D flip-flop that bit lives between clock edges: a value sits on the D input, and the Q output holds the value written during the previous edge. With no clock, the flip-flop keeps Q and ignores D. That is how you get a circuit where two identical inputs produce different outputs depending on when you looked.

Everything else in a stateful device grows out of that single bit. An eight-bit register is eight flip-flops sharing a clock. A program counter keeps the instruction number in flip-flops and, on every edge, increments it or loads an address from the bus. RAM keeps in its cells what was written on an earlier edge and returns the contents of a cell by address. Notice that reading a cell is no different from combinational logic; memory lives only at the moment of writing.

How to tell on a schematic

The sequential part has two signs on a schematic. The first is feedback: an output that returns to an input. The second is a clock input, marked with a symbol like a triangle or a letter with a bar over it. If a schematic has a Clock input and an output that returns to an input, everything between them is the sequential part. If a block has no clock input and none of its lines come back, you are looking at combinational logic.

The feedback loop is not a mistake but a sign of state. The only place in a processor where state changes without a clock is inside the memory array on the die, where contents survive power-down without any clocking around them. The course processor can be run one clock edge at a time by pressing a button, and then a new state is visible by eye, right after the click.

Between registers: why a processor is cut into gates

This is where it becomes clear why a processor needs so many registers. A circuit built entirely of gates with no registers would still produce the right answer, but it would take a very long time to do it: the signal would pass through tens of thousands of gates, each adding its own delay. Instead of one clock period for the whole operation, you would have to wait for the sum of all the delays.

Registers cut the circuit into short combinational sections. Each section is called a pipeline stage, and between the stages sit registers that store the result of the previous stage. While one clock period runs, all the stages work at once, each on its own data. The length of a stage is limited by delay: the shorter the chain of gates, the less time a stage gets. This is where clock frequency comes from: the same processor, cut into more stages, runs faster on the same technology. The cascaded adders in this course are built exactly as stages with registers between them rather than as one giant combinational block, and the anatomy of an adder shows where the boundary falls.

The second consequence of this split: within one clock period a circuit cannot take back a state that has already been written. Everything that has reached a register stays there until the next edge. That is where the compiler's constraint comes from: if two memory accesses follow each other and the second address depends on the result of the first, the processor cannot execute them in one cycle and needs either a stall cycle or a bypass path, described in the article on propagation delay.

How this looks in the simulator

In the simulator of this course, the kind of a node shows up in its behaviour rather than in a label. The NAND, AND, OR and XOR gates, the multiplexer, the decoder, the adder, the comparator and ROM work in a single pass: their output is recomputed while the inputs change. The DFF, register, program counter, index register, pseudorandom sequence generator and RAM store a value between clock edges, so the simulation for them has three phases: first every node computes its new value, then every state is committed, and only then the changes propagate further.

The second sign is visible in the interface: flip-flops, registers and counters show their current value on the body, because the state matters to a person. Gates have no such number, and in the node list they have no Clock input. That alone is what separates a sequential node from a combinational one in the same simulator.

To read the symbols on the sheet, see how to read a schematic, and for how state appears out of gates, see the article on the clock and the D flip-flop. The overall structure is covered in how a processor works.