Level 10: Loopback
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Task
Goal: build an SR latch from NOR gates: S sets the output to 1, R resets it to 0, and with S=0 and R=0 the state is held.
An SR latch is the simplest 1-bit memory cell. Inputs: S (Set — make output 1) and R (Reset — make output 0). Outputs: Q and NQ (inverted).
The main idea: memory is born from feedback: two NOR gates locked onto each other hold a bit because each output feeds an input. Until now every circuit forgot instantly — here state appears for the first time.
Path to this level
The competencies this level develops and their formation levels.
Related Materials
- NOR — RS latch foundation
- How it is built from NAND — the NOR circuit
Solution for self-check
Try building the circuit yourself first. The solution below is a way to check yourself if you're stuck or have already solved it.
What you should get: S=1 sets Q=1, R=1 resets Q to 0, and with S=0 and R=0 the latch remembers the last value.
The simulator has no standalone NOR — build it from OR + NOT: feed the OR output into a NOT. You need two such NORs.
Now the key part — the cross-connection:
- Connect the first NOR's output (Q) to the second input of the second NOR.
- Connect the second NOR's output (NQ) to the second input of the first NOR.
- Feed the first inputs: R to the first NOR, S to the second NOR.
How it works:
- S=1, R=0 → Q=1 (set).
- S=0, R=1 → Q=0 (reset).
- S=0, R=0 → the previous state is preserved. This is memory!
Imagine a 1 that "runs around the loop": each NOR's output feeds the other's input, and vice versa. While S=R=0, no signal tries to knock it out — the circuit "locks" into whatever state it landed in. That is how memory is born from gates: a feedback loop holds the value.
Check yourself
Why does the latch keep its state when S=0, R=0?
Each NOR's output feeds the other's input: the feedback loop sustains the current value by itself.