Decoder V2 (instruction decoder V2)

Inputs

Outputs

How Decoder V2 Differs from the Base Decoder

The protocol is the same: Decoder V2 reads the opcode (the high bits 7:4 of the Instr byte) and stays a combinational circuit with no clock and no memory. What changed is the signal set: twelve outputs instead of nine.

Three differences. First, JZ and JN now have dedicated outputs, JumpZero and JumpNeg. The base Decoder serves both codes (8 and 12) with a single JumpCond output, which makes the two commands indistinguishable in a finished circuit. Second, the ACC_WE signal connects to the accumulator's WE input and enables writes only on the cycles that need them. In the base wiring the accumulator had no load enable and latched a result on every cycle, so programs had to police it by hand. Third, the ready-made ImmOp output selects the immediate operand for LDA; the base wiring assembled the same effect from external NOT and AND gates.

Signal Table

Each row is the complete signal set for one cycle: the accumulator is written only where the table lists ACC_WE, and memory is written only by MemWr.

Wiring the Conditional Jumps

The flags come from the ACC register outputs, not from the live ALU output. The N flag: a Splitter on the ACC bus feeds bit 7 into an AND gate together with JumpNeg. The Z flag: a zero detector (BusZero) on the ACC output, combined by AND with JumpZero. Both conditions and JumpUncond then merge through two OR gates into the program counter's Load input:

AND(JumpNeg, ACC[7]) → OR(JumpUncond, ·) → OR(·, AND(JumpZero, Zero(ACC))) → PC.Load

On a jump cycle ACC_WE is zero, the accumulator holds its value, and the flags are exactly what the last arithmetic left behind. With the base Decoder the flag was tapped from the ALU output during the JN cycle itself: the ALU computed ACC + RAM[label address], so the jump depended on the contents of the cell the label pointed to.

Usage

Decoder V2 is available in the sandbox palette: the "Processor with Assembly" recipe is built on it and executes all 15 commands, including JZ, IX-based indirect addressing, and the LDX/INX family. The base Decoder remains in levels 25–29 and in every saved schematic: old wirings keep working, nothing needs copying over.