Part 5 · RISC Microarchitecture · levels 48–67

The fifth part is RISC Lab: you build a 32-bit RISC processor on the RV32I teaching subset in Verilog and take it to a five-stage pipeline — with forwarding, load bubbles and wrong-path flushes that you detect and resolve yourself.

Open in the game →Course curriculum

The main ideas of the part

A register file instead of an accumulator: 32 registers x0–x31, x0 is always zero; every instruction names its operands explicitly — rs1, rs2 and rd.
The RV32I teaching subset: 32-bit instructions and data, the R/I/S/B/U/J formats, 26 instructions. Memory is reachable only through lw/sw.
The control unit, forwarding unit and hazard unit are Verilog blocks you write yourself: you state the "hazard" and the "bubble" in terms of signals.
Five stages IF—ID—EX—MEM—WB: one instruction walks through all five while its neighbour already stands on the next one.
The engineering trade-off: the pipeline is measured by two metrics — CPI and the cost of the circuit (delay, gate count).

What you will have built by the end

By the end of the part you will have a pipelined RISC core: the single-cycle RV32I core sliced into five stages with forwarding, the load bubble and branch flush — and the same "Knight Rider" LED program that closed the single-cycle arc, now on the pipeline, with a ZIP export for the Tang Nano 9K.

Levels of the part

Each level number leads to its library guide; "Open in the game" goes straight to the level in the simulator.

Up next: the Verilog and FPGA hub →