Level 36: ALU (Verilog)

Task

Build an 8-bit Arithmetic Logic Unit (ALU). When op_code = 0, the module performs addition; when op_code = 1, it performs bitwise AND.

Module ALU8 takes two 8-bit buses (a[7:0], b[7:0]), a 1-bit op_code, and outputs out[7:0] and carry_out.

Use the Adder8 (level 35) and Mux (level 32) modules.

Key insight: in hardware, both results compute in parallel, and an array of multiplexers selects which one reaches the output.

Solution

The ALU is a classic example of hardware parallelism: both results (addition and bitwise AND) are computed simultaneously, and multiplexers select the right one.

Port order of Adder8: (sum, c_out, a, b, c_in). Leave c_in unconnected — it defaults to 0, correct for addition.

Port order of Mux: (out, a, b, sel).

1. Declare two 8-bit buses for intermediate results: wire [7:0] out_add, out_and;
2. Instantiate the 8-bit adder — the addition path: Adder8 adder(out_add, carry_out, a, b);
3. Compute bitwise AND — 8 and gates, one per bit: and aa0(out_and[0], a[0], b[0]); and aa1(out_and[1], a[1], b[1]); … through and aa7(out_and[7], a[7], b[7]);
4. Select the result through 8 multiplexers — all controlled by the same op_code: Mux m0(out[0], out_add[0], out_and[0], op_code); Mux m1(out[1], out_add[1], out_and[1], op_code); … through Mux m7(out[7], out_add[7], out_and[7], op_code);

carry_out is wired directly from Adder8 — it is valid for any op_code.