Decoder
Inputs
| Pin | Type | Description |
|---|---|---|
| Instr | bus8 | Instruction byte — bits 7:4 = opcode, bits 3:0 = operand (ignored) |
Outputs
| Pin | Type | Description |
|---|---|---|
| ALUOp0 | bit | ALU operation select, bit 0 |
| ALUOp1 | bit | ALU operation select, bit 1 |
| MemWr | bit | Memory write enable (1 = write to RAM) |
| JumpUncond | bit | Unconditional jump to PC.Load |
| JumpCond | bit | Conditional jump (if Zero flag = 1) |
| RegLoad | bit | Load accumulator register |
| IXLoad | bit | Load index register (extended I/O addressing) |
| IXInc | bit | Increment index register |
| UseIX | bit | Use index register as memory address source |
How It Works
A conductor plays no instrument, yet without one the orchestra is just noise. The Decoder is the same: it neither computes nor stores, but it reads the opcode (the high bits 7:4 of the Instr byte) and hands out nine control signals. ALUOp0 and ALUOp1 select the ALU operation, MemWr enables writing to RAM, RegLoad enables writing to the accumulator, JumpUncond and JumpCond steer the jumps, while IXLoad, IXInc and UseIX command the index register.
The key property: the Decoder is a combinational circuit — it has neither clock nor memory. Its signals depend only on the current Instr byte and follow it instantly. Example: the byte 0001 0010 splits into opcode 1 (ADD) and operand 2; the decoder raises ALUOp = 00 (addition) and RegLoad = 1, while the operand slips past the decoder into the ALU.
A nuance: opcodes 0 (NOP) and 15 (HLT) put zeros on all nine outputs. The difference is in the aftermath: NOP means "do nothing for one tick" and the program moves on, while HLT is the halt command — the circuit freezes until Reset fires.
Examples (instruction byte → signals)
| Instr (bin / dec) | Opcode | Command | Key signals |
|---|---|---|---|
| 0001 0010 (18) | 1 | ADD 2 | ALUOp = 00 (addition), RegLoad = 1 |
| 0110 0101 (101) | 6 | STA 5 | MemWr = 1 — write the accumulator to RAM |
| 0111 0100 (116) | 7 | JMP 4 | JumpUncond = 1 — jump the program counter to 4 |
| 1001 0000 (144) | 9 | LDX 0 | IXLoad = 1 — load the index register |
In all four rows the low bits (the operand) pass by the decoder: it only looks at the high nibble.
Usage
Level 15 takes instruction decoding apart, level 17 has you build the Decoder from gates by hand, and from level 18 it works as a ready-made block inside the full processor. It is the translator from the language of commands (ADD, STA, JMP and the rest) into the language of control signals the rest of the circuit understands.
The concrete wiring inside the CPU: ALUOp0 and ALUOp1 — to the ALU8 operation select; RegLoad — to the accumulator's WE; MemWr — to RAM's WE; JumpUncond and JumpCond, together with the zero flag, — to the program counter's Load; IXLoad, IXInc and UseIX — to the index register and the address multiplexer.
Related components
Related articles
Frequently Asked Questions
What does the instruction decoder do?
It turns the opcode into control signals: which registers to read, where to write and what the ALU should do.
Why doesn't the Decoder need a clock?
It is combinational: it stores no state, so its outputs faithfully mirror the current instruction byte. Clocking is only needed for elements with memory.
Which signals control the index register?
IXLoad — load (the LDX command), IXInc — increment (INX), UseIX — indirect addressing: read or write at the address held in IX (LDAX, STAX).