Level 30: Word Becomes Hardware

Task

In Verilog, code is not an algorithm — it is a circuit blueprint. Call the basic AND gate to connect wires.

Module AndGate has two 1-bit inputs (a, b) and one output (out).

Write one line: and gate1(out, a, b);

Solution

Simply call the and primitive:

and gate1(out, a, b);

The output (out) comes first, then the two inputs (a, b). The instance name gate1 can be anything.