RISC Microarchitecture: the next course stage

In development — levels 48–56 are announced; no dates have been set.

After 47 levels you can build a computer that runs a program. The next step is to make it fast: split one instruction into five stages and find out where, and why, a pipeline goes wrong.

What changes after Part 4

In Parts 1–4 you built the processor around an accumulator: almost every instruction read it, did something with it, and wrote it back. That is convenient for the first steps and inconvenient for speed, because two instructions cannot work at once while both hold the same register.

Part 5 rebuilds the machine around a different model:

• A register file instead of an accumulator. Eight registers R0–R7; R0 always reads as zero and writes to it are ignored, so a separate zero source disappears.
• Load-store memory access only. Arithmetic and logic work on registers, while LW and SW move values between registers and memory.
• 16-bit instructions and data. The stage architecture is called E-RISC-16: one width for the instruction, the address, and the data.
• Five stages. Fetch, decode, execute, memory access, write-back: IF — ID — EX — MEM — WB. One instruction goes through all five while its neighbour sits in the next one.
• Open control. The Control Unit, Forwarding Unit, and Hazard Unit are built from gates and multiplexers, like the ALU in Part 1. They are not ready-made blocks but circuits you design.

The exact instruction list and opcode table are not fixed yet: they are being refined together with the levels.

Three principles of the stage

The Part 5 levels work differently from those in Parts 1–2. There, the check compared a circuit against a truth table. Here the mistake is usually not in a single gate but in how the stages agree with each other, and it shows only in behaviour over time.

1. Productive failure. First you build a naive pipeline and run a real program on it. The result is wrong. Then you look for the cause in the waveform: which stage, on which cycle, received the wrong value. The rule appears as a conclusion from observation, not as a ready answer in the task.
2. Open control logic. The Control Unit, Forwarding Unit, and Hazard Unit are circuits you build. What counts as "the source is ready", "a conflict", or "a bubble" is something you state in terms of signals rather than take on trust.
3. Engineering trade-off. A pipeline is not free: it speeds up some programs and complicates the circuit. Every step tracks two metrics — cycles per instruction (CPI) and circuit cost: propagation delay and gate count.

The route: nine levels

The sequence runs from the register file to core assembly: each level adds exactly one reason a pipeline can go wrong.

Learning outcomes

After the stage a student can:

• explain what happens in each of the five stages and what the pipeline registers hold;
• read a pipeline diagram: which instruction is in which stage on which cycle;
• tell apart the three kinds of hazard — RAW, load-use, and control — and not confuse their causes;
• derive forwarding, stall, and flush rules from observed behaviour instead of memorising a list;
• compute CPI and compare the single-cycle and pipelined versions of the same machine;
• carry the model over to any RISC-like instruction set.

For teachers

Part 5 follows Part 4 and builds on it: by then the student has already built a control unit, a custom instruction set, and a datapath in Verilog. The pipeline introduces no new gates; it introduces a new requirement on how familiar blocks are organised.

Productive failure works here like a lab session: the right answer cannot be guessed, only derived from the mismatch between the expected and the actual result. What is assessed is therefore not "wire it according to the cheat sheet" but diagnosis: did the student find the cycle, the stage, and the signal where the error appeared, and state the rule that removes it?

Open control logic gives a second point of assessment: the forwarding rule, the stall condition, and the flush point must be written in terms of the circuit's signals. Such a rule can be tested on new programs, not only on the one where it was invented.

The schedule of the stage and the exact instruction set are not fixed. Materials will appear in the course curriculum and the level map together with the finished levels.

Status and scope

• Levels 48–56 are not playable: in the level map and the curriculum they are marked "in development".
• There are no guides for these levels, and no links to them from the course.
• No dates have been announced.
• The basic E-RISC-16 parameters — 16-bit instructions and data, eight registers, five stages — are fixed; the opcode table and the final instruction list may still change.
• The target board for level 56 is the Tang Nano 9K; porting the project to it is part of a future level, not an export available now.
• The current course remains a course of 47 levels: progress, certificates, and classrooms count only those.

Next steps

• Course Curriculum — the 47-level timeline and the Part 5 announcement.
• The level map in the game — course parts and the fifth tab with the announcement.
• Verilog and FPGA — how a circuit becomes a chip on a board.
• Level 47 "Create Computer" — the finale of the current course.