Level 32: Mux (Verilog)

Task

Write a 2→1 multiplexer. When sel = 0, output passes a; when sel = 1, output passes b.

Module Mux has three 1-bit inputs (a, b, sel) and one output (out).

Remember: Verilog describes connections — all lines execute simultaneously, not in order.

Related Materials

  • MUX — multiplexer guide

Solution

Mux formula: out = (a AND NOT sel) OR (b AND sel).

  1. Declare three internal wires: wire nsel, w1, w2;
  2. Invert sel to nsel: not u1(nsel, sel);
  3. AND gate for a with inverted select: and u2(w1, a, nsel);
  4. AND gate for b with direct select: and u3(w2, b, sel);
  5. Combine through OR: or u4(out, w1, w2);

Exactly one of the two AND gates outputs 1 — the one whose control input is active. The other always outputs 0, so the OR honestly passes the right signal.