RISC-V architecture: an open processor standard in plain language
RISC-V is an open processor instruction set standard proposed in 2010 at the University of California, Berkeley, and published in 2014. The word "open" is literal: anyone can read the specification and implement it, there is no fee for the right to build a processor to that standard, and custom extensions can be added on top of the base set. Below is how the standard is put together, how it differs from x86 and ARM, and how it relates to the teaching processor in this course. The bigger map of the field, of which processor architecture is a part, is on the Circuit Design page.
How RISC-V differs from x86 and ARM
The main difference is not the instruction set but the rights to it. The x86 and ARM standards are closed: the specifications belong to companies, and a chip maker buys a licence. The practical consequence is that nobody has produced an x86-compatible processor without a licence in decades, while an architecture with an open specification produces a different market for processors.
| Property | x86 | ARM | RISC-V |
|---|---|---|---|
| Who owns the standard | Intel and AMD, both under licence | Arm Holdings, per-core licence | RISC-V International, open specification |
| Core licence cost | Depends on the agreement | Yes, including free tiers | None |
| Custom extensions | Inside the company only | Custom blocks under the Arm Custom Instruction licence | Allowed, including non-standard ones |
| Where it appears | Computers and servers | Phones, servers, microcontrollers | Microcontrollers, embedded systems, education |
RISC-V has one limitation and it is substantial: a specific chip built to this standard does not have twenty years of accumulated software behind it. An open specification solves a problem a closed one cannot, and does not solve a problem the closed one already solved.
What the base set contains
The core of the standard is called RV32I for 32-bit machines and RV64I for 64-bit ones. It has 32 general-purpose registers, the register numbered one is x0, and it is hardwired to zero: you cannot write a one into it, but you can use it as a constant in a computation. The current ratified version of the base specification came out in 2024.
Everything added on top of the base set is packaged as extensions with letter names, which lets a profile be assembled for a task.
| Extension | What it adds |
|---|---|
| M | Multiplication and division |
| A | Atomic memory operations: multithreading and locks without locking the bus |
| F and D | Floating point at 32 and 64 bits |
| C | Compressed 16-bit instructions: saves memory and die area |
| B | Bit manipulation: single instructions instead of chains of AND, OR, shifts |
| V | Vector operations |
This scheme explains why the words "a RISC-V processor" mean nothing in particular. A microcontroller with the base set plus M, a server core with A, F, D, and V, and a teaching core with I alone are three different machines on one standard. Non-standard extensions exist too: a manufacturer adds its own instructions, and its processor stops being compatible with other people's while remaining RISC-V to itself.
How an instruction is laid out
A base-set instruction occupies 32 bits, and those bits are distributed by function: first the operation code, then the registers and the way they are used. The teaching processor in this course is more modest, with 8 bits per instruction, 4 for the operation code and 4 for the operand. The comparison shows more than any description.
The course teaching machine next to RISC-V
The processor you build in this course has nothing to do with RISC-V: it has 8-bit registers, 15 instructions, Harvard architecture with separate instruction and data memory, and accumulator-plus-constant arithmetic. The comparison is still useful, because it shows which decisions RISC-V makes differently.
| Task | Course teaching processor | RV32I |
|---|---|---|
| Load from memory | LDA 5 by address | lw, lb register plus offset |
| Store to memory | STA 5 | sw, sb |
| Add | ADD 3 constant into the accumulator | add rd, rs1, rs2 three registers |
| Subtract, multiply | SUB 3, no multiply | sub, mul in the M extension |
| Exclusive OR | No instruction, built from AND, OR, NOT | xor, xori in the base set |
| Conditional branch | JZ, JN by the sign of the result | beq, bne by comparing registers |
| Stop | HLT | ebreak is a trap, not a normal halt |
The same task in two syntaxes: add data held in memory and store the result.
; course teaching processor
LDA 5 ; load cell 5 into the accumulator
ADD 3 ; add the constant 3
STA 7 ; store the result into cell 7
HLT ; stop
; RISC-V, RV32I
lw t0, 20(x0) ; t0 = memory[x0 + 20]
addi t0, t0, 3 ; t0 = t0 + 3
sw t0, 28(x0) ; memory[x0 + 28] = t0
ebreak ; a trap that stops the debuggerThe differences show up line by line. In RISC-V the result lives in a register, the operand is chosen by register, and the number 3 travels alongside an add-immediate instruction. The teaching machine has a single accumulator, and the address is encoded in the operation code, so an operand in a command is a constant from 0 to 15.
What to learn it with
The practical base is free. RARS, the RV32I assembler and simulator from the University of Cambridge, runs locally from a single file, shows the state of registers and memory at every step, executes a program step by step, and displays instructions in machine code. It is the best way to watch a command turn into bits.
Then, stage by stage. Spike is the cycle-accurate simulator from Berkeley, used as the reference for verifying cores. QEMU supports RISC-V in user mode, which lets a ready-made operating system run. Verilator compiles a processor you wrote in Verilog into a fast simulator, which is the comfortable way to test your own core. On hardware learning specifically, see module hierarchy in Verilog and the Verilog and FPGA hub: in this course the route from code to a real board runs through the Tang Nano 9K.
What RISC-V does not give you
An instruction set standard is not a processor. The description of the commands says nothing about how fast the machine will be: clock rate, pipeline width, cache, and memory come from the implementation, not from the specification. For the same reason RISC-V does not turn an ordinary computer into a RISC-V machine: that needs either a chip with such a core or a simulator that imitates one.
The Ershov Computer simulator is not one of those tools: it executes 15 instructions of a teaching processor, not RV32I instructions. The difference between the two machines is not difficulty but purpose. The course teaches you to build a computer from gates, Verilog, and a real printed board, while RISC-V hands you a ready instruction set you can program with right away.
What is RISC-V?
RISC-V is an open processor instruction set standard proposed in 2010 at the University of California, Berkeley, and published in 2014. It is a description of how a processor executes commands, not a finished chip: dozens of companies build their own cores and microcontrollers from that same standard.
How does RISC-V differ from x86 and ARM?
x86 and ARM are closed standards: their specifications and the right to implement them belong to companies, and chip makers pay for a licence. The RISC-V specification is open, there is no licence fee for a core, and custom extensions are allowed on top of the base set. The other side of that: a specific RISC-V chip does not have decades of ready-made software behind it, and it does not replace the processor in your laptop.
Can the Ershov Computer simulator run RISC-V code?
No. The game uses a teaching 8-bit processor with 15 instructions, its own assembler, and a simulator of that machine. Not a single RISC-V instruction is implemented: the simulator shows how a computing machine works in general, not how a specific modern chip works.
Where should I start learning RISC-V?
With the RV32I base set: 32 general-purpose registers, loads and stores, arithmetic, comparisons, branches. Practise in RARS, the free assembler and simulator from the University of Cambridge, which runs locally from a single file and shows the state of registers and memory at every step.
Check yourself
Why does RISC-V have a register x0 that is always zero?
It is a constant wired into the register file. Instead of a separate "load zero" instruction you write the x0 address in the operand field, and the encoding stays uniform. A side effect: writing to x0 is silently ignored, and a value lost inside an expression does not raise an error, it changes the result of the computation.
Why can you not simply install a RISC-V processor in a computer?
Programs compiled for x86 target a specific instruction set, and Windows or Linux for x86 contains code that a RISC-V processor cannot execute. You need an operating system built for RISC-V and applications for it. In practice that means a second operating system and a second set of software, not a processor swap inside the same case.
What does a "RISC-V chip profile" mean?
The set of extensions a manufacturer picked for a core: the RV32I base plus M for multiply and divide, for example. More extensions mean more capability and narrower compatibility with programs written for the base set alone. That is why RISC-V has no "processor in general": there are specific cores with specific profiles.
For a processor at the gate level, read how a processor works; for the difference between programming and hardware design, see why Verilog is not programming; for the scale all of this adds up to, see how many transistors a processor has.