Level 43: Engineering Debug (Verilog)

Task

The FullAdder module has a bug — one of the wires is connected incorrectly. Some tests fail. Find the error, fix it, and get all tests passing.

File fulladder.v is editable. cpu.v and testbench.v are read-only (context). Use the tabs to switch between files.

Hint: look closely at gate g4 — which signal should it process for correct carry generation c_out?

Related materials

Full Adder — classical schematic
Verilog Is Not Programming — thinking in circuits

Solution

In file fulladder.v, the error is in gate g4:

and g4(w3, w1, w2);  // bug — third port is w2 instead of c_in

Fix:

and g4(w3, w1, c_in);  // correct — w3 = w1 AND c_in

Signal w3 contributes to the output carry: c_out = w2 OR w3, where w2 = a AND b. Full formula: c_out = (a AND b) OR ((a XOR b) AND c_in) — the classical full adder logic. Using w2 instead of c_in produces incorrect results.