Level 35: Adder8 (Verilog)

Task

Write an 8-bit adder (Adder8) in Verilog. It adds two 8-bit buses a[7:0] and b[7:0] with carry-in c_in. Outputs: sum[7:0] and carry-out c_out.

Use 8 instances of the FullAdder module (from level 34) connected in a ripple-carry chain.

Solution

An 8-bit adder is a chain of 8 full adders where each one's carry-out feeds the next one's carry-in. The carry "ripples" from the least significant bit to the most significant bit (ripple carry).

Port order of FullAdder: (sum, c_out, a, b, c_in).

1. The boilerplate already declares a carry bus: wire [7:0] c;. Add wire w; for the output buffer.
2. Bit 0 (least significant) takes the external c_in: FullAdder fa0(sum[0], c[0], a[0], b[0], c_in);
3. Bits 1–7: each FullAdder gets its carry from the previous one: FullAdder fa1(sum[1], c[1], a[1], b[1], c[0]); FullAdder fa2(sum[2], c[2], a[2], b[2], c[1]); and so on up to fa7.
4. The final carry c[7] needs to be buffered through two consecutive NOT gates (double negation doesn't change the signal but provides a buffer): not g1(w, c[7]); not g2(c_out, w);

Bus bit access uses square brackets: a[0], b[3]. All 8 adders work simultaneously — the chain exists in hardware, not in line order.