MUX
Inputs
| Pin | Type | Description |
|---|---|---|
| A | bit | First input signal |
| B | bit | Second input signal |
| Sel | bit | Selector: 0 → A, 1 → B |
Outputs
| Pin | Type | Description |
|---|---|---|
| Q | bit | Sel=0 → A, Sel=1 → B |
How It Works
Picture a railroad switch: two tracks merge into one, and the switch mechanism decides which train goes on. MUX is the same switch, only for bit signals. Two signals arrive at inputs A and B, the Sel input carries the command "who gets through", and exactly one of them appears on output Q.
The key property: Sel = 0 opens the path from A, Sel = 1 — from B. Behind it stands a simple formula Q = (A ∧ ¬Sel) ∨ (B ∧ Sel): signal A is gated through AND by "Sel is zero", signal B — by "Sel is one", and OR merges the results. The unused input is physically locked out by a zero and never reaches the output — switching happens instantly on any change of Sel.
A nuance: a MUX computes nothing and remembers nothing — it only chooses. But arbitrary large switches are built from it: two MUX 2→1 plus one more give 4→1, and a cascade of seven gives 8→1, where a three-bit selector addresses the source. This scalability is what makes the multiplexer the universal router of the processor.
Examples
| Scenario | A | B | Sel | Q |
|---|---|---|---|---|
| A selected, carrying 1 | 1 | 0 | 0 | 1 |
| B selected, but carrying 0 | 1 | 0 | 1 | 0 |
| B selected, carrying 1 | 0 | 1 | 1 | 1 |
| Signals identical | 1 | 1 | 0 or 1 | 1 |
Note the last row: when both inputs carry the same signal, flipping the selector changes nothing — the output simply does not notice the "switch click".
Truth Table
| Sel | A | B | Q |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
Usage
The gateway level is 9, but the MUX's true role unfolds inside the processor. Choosing a data source is its main job: which register drives the shared bus, which value goes into the ALU, which address is sent to RAM — the one from the ProgramCounter or from the IndexRegister. Inside the ALU (level 13) a cascade of multiplexers picks between the adder's result and the logic blocks' results using the opcode bits.
A concrete trick — scaling: two selector bits and three MUX 2→1 give a choice of four sources; three bits and seven MUX — a choice of eight. The same method builds the instruction decoder's routers and bus switches. Whenever data "converges" from two places into one in your circuit, a multiplexer stands in between.
Interactive Demo
Click inputs to toggle value (0 / 1)
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Frequently Asked Questions
How does a MUX pick its input?
The select signal S chooses the source: when S=0 the output is A, when S=1 it is B.
How do you build an 8→1 MUX from 2→1 MUXes?
As a three-tier cascade: four MUXes pair up the inputs, two more pair up the results, and a final one chooses between them. That is seven MUX 2→1 in total, with the three-bit selector acting as the address of the chosen input.
How does MUX differ from BusMUX?
MUX switches individual bits, while BusMUX switches whole 8-bit buses: inside, it repeats the same formula for all eight bits at once.