Ershov Board — Technical Specification

The main problem when working with logic circuits is contact bounce. If we don't suppress it in hardware, a single press of the STEP button will produce 5–6 clock pulses, and the processor will "fly" forward, breaking the entire methodological process.

PCB Design Specification: "Ershov Board" v1.0

1. General Requirements

Device Type: Laboratory Dock Board for the Tang Nano 9K module.

Power: Supplied via the USB Type-C connector on the Tang Nano 9K board itself (no additional power connector on Ershov Board is required; route 5V and 3.3V rails from the dev board pins).

Assembly: All control elements (buttons, switches, rotary switches) are placed on the top layer for convenient operation.

Protection: Mandatory short-circuit protection (fuse/PTC) on the power rail and current-limiting resistors on all I/O pins to protect FPGA ports from student code errors.

2. Component Base and Interfaces

BlockComponentsLayout and Circuit Requirements
FPGA Socket2 × 24-pin female headers (2.54 mm pitch)Footprint matching Sipeed Tang Nano 9K dimensions. Label pins on silkscreen.
Input Bus8 × toggle switches or DIP switchExternal pull-up/pull-down resistors required. Smooth travel for easy switching.
Output Bus8 × LEDs (red/green)Align in a row opposite the Input Bus. Use current-limiting resistors.
STEP Button1 × tactile button (large, durable)Critical: Hardware debounce (RC circuit + Schmitt trigger, e.g. 74HC14). Signal must be perfectly clean.
RESET Button1 × tactile button (different color)Global circuit reset. Hardware debounce recommended.
MODE Switch1 × rotary switch (1 pole, 5 positions)Common contact to GND. 5 signal lines to FPGA pins. Pull-up resistors.
Matrix16×16 LED matrixUse matrices with built-in controllers (e.g., 4 × MAX7219 modules) to save pins. SPI connection (DIN, CS, CLK).
Joystick5-position digital joystick (Up, Down, Left, Right, Press)Analog stick is unsuitable (FPGA has few ADC pins). Use standard digital ground closures.

3. Preliminary Pin Mapping

The Tang Nano 9K (GW1NR-9 chip) has sufficient user I/O pins. The mapping must be fixed so students receive a ready-made .cst constraints file.

GroupPin CountStudent Logic AssignmentNotes
Buttons2clk_step, rst_nClock and reset inputs.
Mode Switch5mode[4:0]Display mode select (PC, IR, ACC, ALU, RAM).
Input Data8switches[7:0]8-bit manual input bus.
Output Data8leds[7:0]8-bit output bus.
Display3matrix_din, matrix_cs, matrix_clkSPI interface for 16×16 matrix.
Joystick5joy_u, joy_d, joy_l, joy_r, joy_pNavigation for the Snake finale.
Total:31 pinsTang Nano 9K has over 32 available pins.

4. Silkscreen and UX Requirements

The board is a teaching aid. Silkscreen is as important as trace routing.

Zoning: Visually divide the board into zones by printed lines: CONTROL (Step, Reset), INPUT (Switches), DEBUG (LEDs and Mode Switch), PERIPHERALS (Matrix and Joystick).

MODE Scale: Positions must be clearly printed around the rotary switch: PC (Program Counter), IR (Instruction Register), ACC (Accumulator), ALU (ALU Out), RAM (Data Bus).

Branding: Print the project logo and board revision in a corner. Recommended solder mask color: classic dark green (evokes industrial engineering associations).

Ershov Loader

The main task of the Ershov Loader is to act as a perfect facade. The student should not even suspect that heavy corporate software (Gowin EDA) runs under the hood. To them, it should be a one-button "Program Chip" utility with a clean, understandable log.

Under the hood, we will use the Gowin command-line interface (gw_sh) for synthesis and the open-source openFPGALoader utility for programming, as it works via USB much more reliably than the proprietary programmer.

Utility Architecture

Engine: The application can be written in Python (with a simple Tkinter or PyQt UI) or compiled as a lightweight Go/Rust binary (to avoid dependency overhead).

Bundled Dependencies:

  1. Gowin CLI (gw_sh and synthesis binaries — these can be extracted from the full Gowin EDA, bringing the utility from 2 GB down to about 100–200 MB).
  2. openFPGALoader (programs Tang Nano 9K reliably from the command line).

Pipeline Algorithm

1. Extraction and Validation: The utility receives the Ershov_Computer.zip archive. Extracts it to a temp directory. Checks for top.v (main module) and Ershov_Board.cst (constraints). If anything is missing, shows a human-readable warning.

2. TCL Script Generation: To avoid opening the Gowin GUI, the loader generates a build.tcl script on the fly with commands to select the chip, add .v files, add .cst, and run synthesis and place-and-route.

3. Background Synthesis (Log Parsing): The loader runs gw_sh build.tcl. Gowin EDA spews thousands of lines of technical text. The loader intercepts stdout and acts as a filter/translator. The student sees only nicely animated statuses: "Reading blueprints…" → "Synthesizing logic gates…" → "Routing wires inside the chip…".

4. Results Analysis: If compilation succeeds, the loader parses the report file (.rpt) and shows the student cool statistics about their processor before programming: LUTs used, registers used. The student understands how "big" a computer they built.

5. Programming into Silicon: The loader finds the generated bitstream project.fs. Runs the background command: openFPGALoader -b tangnano9k project.fs. The progress bar reaches 100%. A message appears: "The computer is alive! You can press the STEP button on the board."

Error Handling (Frustration Protection)

The biggest problem with EDA systems is terrible error messages. If a student forgets a semicolon, Gowin can spew 50 lines of unreadable red text. The Ershov Loader must intercept common compiler errors via regex and translate them into human language.

Examples: