Level 34: FullAdder (Verilog)

Task

Write a full adder in Verilog. It adds three bits: a, b, and carry-in c_in. Outputs are sum and carry-out c_out.

You may use the HalfAdder module from the previous level — a great chance to practice module reuse.

Remember: Verilog is not a program — it describes a circuit. All lines run simultaneously.

Solution

A full adder is easily built from two half adders (module HalfAdder from level 33) and one OR gate.

Port order of HalfAdder: (sum, carry, a, b).

1. Declare three internal wires: wire sum1, carry1, carry2;
2. First half adder adds a and b: HalfAdder ha1(sum1, carry1, a, b);
3. Second half adder adds sum1 and c_in: HalfAdder ha2(sum, carry2, sum1, c_in);
4. Combine both carries through OR: or g1(c_out, carry1, carry2);

The first half adder produces an intermediate sum sum1 and a first carry carry1. The second gives the final sum sum and a second carry carry2. The two carries are never both 1 — OR safely combines them.

Alternative: build FullAdder from 5 primitives (2×XOR, 2×AND, 1×OR) — try both approaches!