Teaching Silicon Math (The Secret of '+')

In any programming language, addition looks like magic. You simply write sum = a + b, and the processor instantly gives the correct answer. It seems like a little bookkeeper sits inside the computer, someone who knows the rules of arithmetic.

The Verilog half adder in the RTL viewer: XOR for sum, AND for carry
The half adder in the RTL viewer

But in reality, silicon can't count. It has no built-in understanding of math. All we have at the basic level is current, voltage, and logic gates (AND, OR, NOT, XOR).

The + sign in code is a high-level illusion. At the Structural Verilog level you'll have to build, with your own hands, a circuit that makes dumb transistors simulate addition.

How to Add Two Bits?

Imagine that two signals (bits) come to us along two wires: A and B. Our task is to add them. Let's recall school math in binary. There are only four possible situations:

So far everything is simple. The result fits perfectly into one output wire. But what happens if both inputs have ones?

The answer consists of two digits! This means that to add just two wires, one output pin physically won't be enough. There must be two of them:

  1. Sum — this is the least significant bit (the right digit of the answer).
  2. Carry — this is the most significant bit (the left digit of the answer, which "carries over" to the next digit, like in column addition).

The Iron Logic of Arithmetic

Now let's look at these two outputs as engineers armed with logic gates.

First, let's deal with the Sum output (the least significant bit): Look at the results of 0+0, 0+1, 1+0, and 1+1. The least significant bit equals 1 only when the inputs are different (one is 0, the other is 1). If the inputs are the same (both 0 or both 1), the least significant bit equals 0. Do you recognize the pattern? This is the perfect description of the Exclusive OR gate (XOR)!

Conclusion: To get the sum bit, we simply need to run wires A and B through a xor gate.

Now let's deal with the Carry output (the carry bit): In what single case do we get a carry of one into the next digit? Only when two ones are added (1+1). That is, the carry equals 1 only if A = 1 AND B = 1. Familiar logic? This is the classic logical AND (AND) gate.

Conclusion: To get the carry bit, we need to run the same wires A and B through an and gate.

The Birth of the Half Adder

You have just invented one of the most important microchips in the history of computing — the Half Adder.

Why is it called "Half"? Because it can only add two initial bits. If we want to add larger numbers in a column, we'll need a circuit that can also accept a third bit (the carry from previous computations). But we'll talk about that next time.

In level 33 your task is to transfer this logic into Verilog code. You need to declare a HalfAdder module with two inputs and two outputs, and then, inside it, call two built-in gates (xor and and) at the same time, connecting the wires to them correctly. This is where real circuit design begins!

Try it in the simulator →