Teaching Silicon Math (The Secret of '+')

In any programming language, addition looks like magic. You write c = a + b, and somehow the machine produces the correct sum. The mechanism is hidden behind a single character, and most programmers never peek behind the curtain. But when you design hardware, you are the curtain. You must build the circuit that makes + happen.

Let's start with the simplest possible addition: adding two single bits. In binary, there are only four cases:

• 0 + 0 = 0 (no carry)
• 0 + 1 = 1 (no carry)
• 1 + 0 = 1 (no carry)
• 1 + 1 = 0, carry 1 (in decimal: 1 + 1 = 2, written as binary 10)

Notice something? The sum bit (the rightmost digit) is 1 exactly when the two inputs differ. When they're the same (both 0 or both 1), the sum bit is 0. That's the exact behavior of an XOR gate — exclusive OR, which outputs 1 only when its inputs are different.

The carry bit (the "one in your head") is 1 only when both inputs are 1. That's an AND gate.

So to add two bits, you need exactly two gates: one XOR for the sum, one AND for the carry. This circuit is called a Half Adder.

In Verilog:

module HalfAdder(
    output sum,
    output carry,
    input a,
    input b
);
    xor g1(sum, a, b);
    and g2(carry, a, b);
endmodule

That's it. Seven lines of Verilog, two gates, and you've built the foundation of all arithmetic in every processor ever made. When you plug input A into both gates — the XOR and the AND — the current splits at the fork and flows into both gates simultaneously. The XOR computes the sum bit; the AND computes the carry bit. Both results are valid at the same instant, every instant.

Why is it called a "Half" Adder? Because it's incomplete. Real addition often involves three inputs, not two: the two bits being added plus a carry coming in from a previous, less significant bit. The Half Adder has no carry-in port. It can only add two isolated bits.

Think of it this way: imagine you're adding 11 + 01 on paper:

  11
+ 01
----
 100

You start from the rightmost column: 1 + 1 = 0, carry 1. But the next column is 1 + 0 + (carry 1) = 0, carry 1. That third input — the carry from the previous column — is exactly what the Half Adder can't handle. For that, you need the Full Adder, which we'll build in the next article.

Level 33 ("HalfAdder in Verilog") is your chance to wire up these two gates yourself. When you see the truth table match — sum always XOR, carry always AND — you'll never look at a plus sign the same way again.