Level 41: Big Project (Verilog)

Task

Build the top-level CPU module by instantiating three submodules: eight full adders FullAdder and a register Reg8. The module code is in separate file tabs — this is a multi-file project (VFS).

The CPU module takes clk, two 8-bit numbers a and b, and outputs out (stored value of b), sum (a + out), and carry (overflow flag = NOT c[7]).

Use: FullAdder (from fulladder.v) — sum, c_out, a, b, c_in; Reg8 (from register.v) — out, in, clk. Chain of adders: fa0…fa7 with carry c[0]…c[6]. Register stores b on clk edge. not g1(carry, c[7]);

Switch files via tabs above the editor. cpu.v is editable, others are read-only.

Related materials

Verilog Hierarchy — module instantiation
Verilog Buses — 8-bit wires

Solution

The CPU consists of a chain of 8×FullAdder (summing a + out) and a Reg8 (storing b):

Declare carry wires: wire [7:0] c;
8 full adders with ripple carry:
FullAdder fa0(sum[0], c[0], a[0], out[0], 1'b0);
FullAdder fa1(sum[1], c[1], a[1], out[1], c[0]);
…
FullAdder fa7(sum[7], c[7], a[7], out[7], c[6]);
Register: Reg8 reg_acc(out, b, clk);
Carry flag: not g1(carry, c[7]);

Port order for FullAdder: (sum, c_out, a, b, c_in). Port order for Reg8: (out, in, clk).