Part 3 · Verilog · levels 30–43

The main ideas of the part

• Verilog is not programming: a line describes connections, not a sequence of actions.
• Module and ports: the interface matters more than the insides — a FullAdder is built from two HalfAdders, and you cannot see it from outside.
• A bus is a vector of bits; a generate loop replicates one module across all the bits.
• Sequential circuits change only on the clock edge: DFFs, counters, RAM.
• RTL Viewer shows what the simulator built from your text; the waveform shows how signals behave tick by tick.

What you will have built by the end

By the end of the part you will have described the whole processor datapath as text — registers, ALU, RAM — and assembled a multi-file project out of reusable modules.

Levels of the part

1. 30. Hello, Wire! — explain that Verilog describes a circuit, not an algorithm, and instantiate a gate Open in the game →
2. 31. Exclusive OR (XOR) — explain Verilog statement parallelism and build an XOR from and/or/not without the xor primitive Open in the game →
3. 32. Flow Control (MUX) — translate a circuit problem (MUX) into structural Verilog Open in the game →
4. 33. First Computation (HalfAdder) — build a half adder in Verilog (XOR + AND) Open in the game →
5. 34. Module Hierarchy (FullAdder) — explain module hierarchy and reuse your own HalfAdder Open in the game →
6. 35. Data Buses (Adder8) — build an 8-bit adder by instantiating 8 FullAdders Open in the game →
7. 36. ALU — build the ALU in structural Verilog (8×and, 8×Mux), pass the structural check, and explain how the code maps to the architecture Open in the game →
8. 37. Memory and Time — build a memory module from dff and generate-for, and demonstrate why the memory needs clk while the ALU does not Open in the game →
9. 38. Step by Step — build a feedback counter broken by D flip-flops; use 8'b constants Open in the game →
10. 39. Random Access Memory — wire the built-in RAM256 and explain the black-box abstraction Open in the game →
11. 40. Heart of the CPU — build a datapath (Counter → ROM → ALU → Register) and explain the data path Open in the game →
12. 41. System Anatomy — assemble a CPU from read-only library modules in a VFS project and explain the roles of the library files Open in the game →
13. 42. X-Ray for Silicon — debug hierarchy with RTL Viewer drill-down and find a misconnected primitive Open in the game →
14. 43. Freezing Time — read a timing diagram and find and fix an error in the circuit Open in the game →

Each level number leads to its library guide; "Open in the game" goes straight to the level in the simulator.