Level 39: RAM (Verilog)

Task

Wrap the built-in RAM256 module — a 256-cell memory with 8-bit data. The module writes data to an address (on rising edge of clk when we = 1) and reads data (combinational, at any time).

Module MemoryCell takes: we (write enable), addr[7:0] (address), data[7:0] (write data), clk. Output: q[7:0] (read data).

Solution

1. Instantiate RAM256: RAM256 mem(clk, we, addr, data, q);

RAM256 port order: (clk, we, addr, data, q) — exactly five ports.

• clk — clock (writes on rising edge)
• we — write enable (1 = write, 0 = read)
• addr[7:0] — 8-bit address
• data[7:0] — 8-bit write data
• q[7:0] — 8-bit read data

Reading is combinational: q always reflects the content of cell at addr. Writing occurs on the rising edge of clk: if we = 1, data is written to cell addr.