Propagation Delay: Why Signals Arrive Late

In an ideal circuit world, all signals would change instantly: flip an input and the output flips in the same nanosecond. In reality, every gate takes a small but nonzero time to switch. This time is called propagation delay, and it is why signals "arrive late".

Every gate is a small delay

A logic gate is a physical device. When the voltage on its input changes, the transistors inside need time to switch: to charge or discharge capacitances and stabilize the output. This takes picoseconds or nanoseconds, depending on the technology.

The key consequence: delays add up. If a signal passes through a chain of 10 gates, the total delay is 10 times greater than for a single gate.

The adder carry chain

The best example is a multi-bit adder. Recall how it works: each full adder adds two bits and the carry from the previous digit. Each block's CarryOut feeds the CarryIn input of the next one.

This forms a chain: to know the carry at the output of the last digit, you must first compute the carry in the first digit, then the second, and so on up to the eighth. Each step adds a couple of gate delays. So the carry signal ripples through every block in the chain.

What about the sum? The low sum bit Sum[0] depends only on the inputs A[0] and B[0] — there is no carry chain on its path, so it is ready almost immediately. But in the higher digits the sum bits wait for the carry from the previous stages just as the final carry does: Sum[i] = A[i] ⊕ B[i] ⊕ CarryIn[i]. Until the carry reaches a digit, the sum bit in it has not settled.

The carry chain: every full adder (FA) adds its own delay Δ — the high digits wait for the carry from the low ones

What it looks like on a timing diagram

In the simulator (and on a real oscilloscope) this shows up as follows: on the diagram, the carry Carry settles later than the lowest sum bit Sum[0]. Not because the sum is computed "faster" or "first", but because the carry has a longer path: more gates between input and output. The higher sum bits change together with the carry.

If on level 43 "Freezing Time" the carry output appears with a delay relative to the sum — that is not a simulator bug. It is a real effect of real circuits, and the more digits the adder has, the more noticeable the carry lag.

Why it matters

The clock frequency is limited by the longest path. A processor must wait until the slowest signal settles — otherwise the next clock tick begins before the circuit has stabilized.
The longer the carry chain, the slower the adder. That is exactly why carry-lookahead adders exist: they compute the carries in parallel.
Delay is not a bug — it is a property of physics. Understanding it explains why digital circuits are designed carefully and why clocking matters so much.