Level 31: Hello, Wire!

Task

Build an XOR gate using only and, or, and not. The built-in xor primitive is disabled.

Module MyXor has two 1-bit inputs (a, b) and one output (out).

Key rule of Verilog: lines of code describe physical connections — they all run simultaneously, not top-to-bottom.

Related Materials

  • XOR — exclusive OR gate
  • AND — conjunction gate
  • OR — disjunction gate

Solution

XOR can be expressed through AND, OR, and NOT: XOR = (A AND NOT B) OR (NOT A AND B).

  1. Declare internal wires on one line: wire nota, notb, w1, w2; — they connect gate outputs to other gate inputs.
  2. Invert a into nota: not g1(nota, a); — first argument is output, second is input.
  3. Invert b into notb: not g2(notb, b);
  4. First conjunction — a AND notb: and g3(w1, a, notb);
  5. Second conjunction — nota AND b: and g4(w2, nota, b);
  6. Combine through OR: or g5(out, w1, w2); — output goes directly to the module port.

All five gates are "wired up" simultaneously — declaration order doesn't matter.