Level 37: Register (Verilog)

Task

Build an 8-bit register from D flip-flops. The register stores 8 bits of data and updates on the rising edge of clk.

Module Reg8 takes an 8-bit bus in[7:0] and a 1-bit clk, and outputs out[7:0].

Use generate-for to instantiate 8 D flip-flops. Each DFF stores one bit: q = d on the rising edge of clk.

Key insight: this is the first sequential level — the simulator processes clock ticks sequentially, and state persists between tests.

Related Materials

  • DFF — D Flip-Flop

Solution

A register is an array of D flip-flops, each storing one bit. Instead of writing 8 lines manually, use generate-for.

  1. Declare the index variable: genvar i;
  2. Open the generate block: generate
  3. Loop over 8 bits: for (i = 0; i < 8; i = i + 1) begin : dff_gen
  4. Inside — one DFF per bit: dff d(out[i], in[i], clk);
  5. Close: end endgenerate

DFF port order: (q, d, clk). Output q becomes out[i], input d is in[i], and clk is shared across all DFFs.