Clock and the D Flip-Flop

Combinational circuits — AND, OR, adders, multiplexers — react instantly to their inputs. Change an input, and the output changes immediately. But a processor can't work on instant reactions alone; it needs to remember things. It needs memory.

The SR latch was already a memory element, but it had a flaw: setting both inputs to 1 caused an undefined state. The D flip-flop solves this elegantly. It has a single data input (D) and a clock input. On the rising edge of the clock signal, the flip-flop captures whatever is on the D input and holds it until the next clock edge. The output Q always shows the captured value.

The clock is the heartbeat of the processor. It's a square wave signal that oscillates between 0 and 1 at a fixed frequency. On each rising edge, all flip-flops simultaneously capture their inputs. Between edges, combinational logic computes new values. The clock ensures that everything happens in lockstep — no race conditions, no chaos.

Practical example. Think of a production line. Items move from station to station on a conveyor belt. Each station does its work on the item in front of it. When the conveyor belt clicks forward, all stations simultaneously pass their completed work to the next station and receive new items from the previous one. The clock is that conveyor belt click. D flip-flops are the storage positions between stations. Between clicks, the ALU (a station) computes; on the click, the result is captured in the register (passed forward).