Bus Conflicts and the Address Decoder

Imagine a road with only one lane, where cars from five different garages all try to drive at the same time. That's a bus conflict. In a processor, RAM, ROM, the ALU, the accumulator, and peripherals all share a single data bus. If two devices try to output data simultaneously, a short circuit occurs — currents collide, and the result is unpredictable garbage.

The address decoder is the traffic controller that prevents this chaos. It receives an address from the processor and determines which device gets to "speak" at this moment. Only one device ever gets the signal to output data; all the others are forced into a high-impedance state — essentially disconnecting from the bus.

The decoder works like a demultiplexer: it takes an N-bit address and activates exactly one of 2^N output lines. Each line is connected to the "output enable" pin of a specific device. When the decoder activates line 3, only device 3 connects to the bus; all others are electrically isolated.

Practical example. In the Ershov Computer, the address space is divided: addresses 0-15 point to ROM, 16-31 to RAM, 240-255 to I/O ports. When the processor reads from address 20, the address decoder sees that it's in the RAM range and activates only the RAM chip's output. ROM stays silent. The bus transmits exactly one value — no conflicts, no ambiguity.