Harvard Architecture

Most modern computers use Von Neumann architecture: a single memory holds both program instructions and data. It's simple and flexible — you can treat code as data and vice versa. But it has a bottleneck: the processor can't fetch an instruction and read data simultaneously because they share the same bus.

Harvard architecture solves this by physically separating instruction memory (ROM) from data memory (RAM). The processor has two independent buses: one for reading instructions, one for reading and writing data. While the ALU processes data from RAM, the program counter can simultaneously fetch the next instruction from ROM.

This parallelism makes Harvard architecture faster for simple, predictable workloads. It's widely used in microcontrollers (like Arduino's ATmega chips), DSPs, and embedded systems where every clock cycle counts. The trade-off is that you can't easily modify program code at runtime — the instruction memory is read-only during normal operation.

Practical example. In the Ershov Computer, the Harvard split is clear: the ROM holds your program (the bytecode assembled from your assembly code), and the RAM holds variables and data. When the processor executes LDA 20, two things happen in parallel: the program counter fetches the next instruction from ROM, while the data bus reads the value from RAM address 20 into the accumulator. With a unified bus, these would have to happen sequentially — doubling execution time.