Level Guides
Step-by-step task descriptions and solutions for all 67 levels — from the first wire to a pipelined processor on an FPGA.
- 1. Let there be light!
- 2. Negation
- 3. Perfect pair
- 4. At least one
- 5. Strict choice
- 6. Half Adder
- 7. Full Adder
- 8. 8-bit Adder
- 9. Crossroads
- 10. Loopback
- 11. Smart memory
- 12. Tangible Memory
- 13. Operation Selection
- 14. Heart of math
- 15. System Pulse
- 16. Program Counter
- 17. Anatomy of a Decoder
- 18. FINALE: The Ershov Computer
- 19. Step Forward (PC+2)
- 20. Dual Read
- 21. Pointers
- 22. Bus Conflict
- 23. Gamepad
- 24. Manual Pixel
- 25. Negative Check
- 26. Dice Roll
- 27. Hello, Ports!
- 28. Moving Dot
- 29. FINALE: Snake
- 30. Hello, Wire!
- 31. Exclusive OR (XOR)
- 32. Flow Control (MUX)
- 33. First Computation (HalfAdder)
- 34. Module Hierarchy (FullAdder)
- 35. Data Buses (Adder8)
- 36. ALU
- 37. Memory and Time
- 38. Step by Step
- 39. Random Access Memory
- 40. Heart of the CPU
- 41. System Anatomy
- 42. X-Ray for Silicon
- 43. Freezing Time
- 44. Control Unit
- 45. My ISA
- 46. Memory-Mapped I/O
- 47. Create Computer
- 48. Farewell, Accumulator!
- 49. Anatomy of an R-type Instruction
- 50. A 32-bit ALU
- 51. A Constant Inside the Instruction
- 52. Memory by the Rules
- 53. A Step of Four
- 54. A Loop on BNE
- 55. Array Sum
- 56. Call and Return
- 57. Nested Calls and the Stack
- 58. Assembling RV32I
- 59. Knight Rider RISC
- 60. The Verification Lab
- 61. Why the Cycle Is Long
- 62. Between Stages
- 63. Five Instructions in Flight
- 64. The Short Path
- 65. The Load Bubble
- 66. Ghosts of the Wrong Path
- 67. Knight Rider Pipeline