Level 61: Why the Cycle Is Long

The task

Goal: build a linear 9-instruction program (lui/addi/ori/sw/lw/add), run it on the reference pipeline, and predict which stage instruction No. 5 occupies on cycle 6. The single-cycle machine did all the work in one long cycle: fetch, decode, ALU, memory and write-back once per cycle. The pipeline slices that path into five short stages (IF → ID → EX → MEM → WB), and instructions move along it like on an assembly line: while one executes, the next is already being decoded. Note: there are more cycles than instructions — the first four cycles only fill the pipeline, the last four drain it. The Race Track on the platform shows every instruction in its stage.

Until now your programs ran on a single-cycle core: one instruction, one cycle, because the entire path (fetch, decode, ALU, memory, write-back) fit into one long cycle. From this level on, programs run on a pipeline — five short stages: IF (fetch) → ID (decode and register read) → EX (execute) → MEM (memory) → WB (write-back). Instructions move through the stages like on an assembly line: while one executes, the next is already being decoded.

No schematic to build — this is a programming level, following 54–59. The tasks:

Build a linear 9-instruction program (no branches, no cross-cycle dependencies): base lui x5, 0x1, data addi x6, x0, 7 and addi x7, x0, 20, constant ori x8, x0, 0x7F0, store sw x6, 0(x5), read-back lw x9, 0(x5), arithmetic add x10, x6, x7, sw x10, 4(x5), add x11, x9, x10.
Predict the stage. The first "Check" asks: which stage will instruction No. 5 occupy on cycle 6? Count it yourself: instruction No. 5 is fetched on cycle 5, and each following cycle moves it to the next stage.
Run it on the pipeline. The platform shows the Race Track: five lanes, one per stage; press "Step" and watch the instruction capsules move right. Click a capsule for the instruction card.
Explain the numbers. 9 instructions — yet 13 cycles: the first four cycles only fill the pipeline (fill), the last instructions reach WB after the halt (drain). The .end halt still retires nothing and adds no cycle.

Solution for self-checking

Write the program yourself first. The solution below is a checkpoint.

What you should get: the 9-instruction program takes 13 cycles (9 retirements + 4 fill); the prediction is confirmed: instruction No. 5 is in the ID stage on cycle 6; final values: x11 = 34, memory 0x1000 = 7 and 0x1004 = 27.

Step 1 — the golden program.

lui  x5, 0x1        # 0:  base 0x1000
addi x6, x0, 7      # 4
addi x7, x0, 20     # 8
ori  x8, x0, 0x7F0  # 12
sw   x6, 0(x5)      # 16: DMEM[0x1000] = 7
lw   x9, 0(x5)      # 20
add  x10, x6, x7    # 24: 27
sw   x10, 4(x5)     # 28: DMEM[0x1004] = 27
add  x11, x9, x10   # 32: 34
.end                # 36: halt

Step 2 — checkpoint numbers. Run: 9 instructions = 9 retires, 13 cycles (9 + 4 fill cycles), halt at PC = 36. Final registers: x5 = 0x1000, x6 = 7, x7 = 20, x8 = 0x7F0, x9 = 7, x10 = 27, x11 = 34; memory: 0x1000 = 7, 0x1004 = 27. No bubbles: the program is linear, without load-use (x9 is used three instructions after the lw) and without branches.

Step 3 — the prediction. Instruction No. 5 (sw) — cycle 5: IF, cycle 6: ID (the answer is 2), cycle 7: EX, cycle 8: MEM (the store), cycle 9: WB.

Step 4 — why not 5×. A short program pays 4 fill cycles and saves nothing on drain: 13 > 9. In a long loop (counter or array_sum on the following levels) the fill amortizes over dozens of retires and the pace approaches "one instruction per cycle" — with a cycle several times shorter than the single-cycle one.

Check yourself

Why is the pipeline not 5 times faster than the single-cycle core?

A short program pays the fill and drain in full: 13 cycles against 9 retirements. The win shows up on a long instruction stream — a loop, where the 4 fill cycles amortize over dozens of instructions.