A hands-on course in digital logic and computer architecture for schools, colleges and universities
«Ershov Computer» is a free browser-based course where students build a computer from scratch: from logic gates and an adder to a processor, assembler, Verilog and an FPGA project. Use it as an elective, after-school activity, lab practicum or levelling module before a core discipline.
Problem and solution
Digital logic and computer architecture are hard to teach without practice: schools rarely have hardware, and university labs need expensive FPGA boards and benches.
Problem
- Not enough hands-on practice: theory "about computers" without actually building one.
- Outdated software and virtual machines that fail on modest PCs.
- Scattered materials: no single course with automated solution checking.
Solution
- 47 levels with automatic checking — from a NAND gate to a working processor.
- Everything runs in an ordinary browser: no installation, no IT burden.
- A single course curriculum with a measurable outcome for every level.
What students learn
Four parts take a student from basic logic to designing their own computer. The course curriculum is a timeline of all 47 levels with the task, difficulty and outcome of each.
Basics
AND, OR, NOT gates, adders, flip-flops, registers and building an 8-bit Harvard processor.
Advanced Architecture
Addressing, buses, peripherals, assembler and the final "Snake" project.
Verilog
Verilog — a widely used hardware description language: primitives, modules, buses, RAM and datapath.
Computer Design
Control unit, your own instruction set and export to the Tang Nano 9K FPGA.
Which institutions and disciplines it fits
School: grades 7–11
An elective, after-school activity, engineering or IT class, club or summer school. The course deepens the computer science topics of logic fundamentals, computer architecture, number systems and algorithms — without replacing the core school curriculum.
- A solid base for informatics olympiads and career guidance in microelectronics.
- The game-like format with instant feedback keeps even poorly motivated students engaged.
College / Vocational
A hands-on module for "Fundamentals of Digital Electronics", "Digital Circuit Design", "Hardware Architecture" and related courses — depending on the curriculum and major.
- A lab practicum with automatic checking.
- An introductory module before microcontrollers and FPGAs.
- Can be included in the optional/variable part of the programme.
First year of university
An introductory practicum or lab module for "Computer Architecture", "Computer Organization", "Digital Logic" and related courses; especially useful for levelling a group.
- Parts 1–2 give an intuitive model of a computing system.
- Parts 3–4 introduce structural Verilog, timing diagrams and FPGA export.
A teacher chooses the depth of implementation: passing all 47 levels is not required. Trajectories and volumes are in the table below; the topic, duration and measurable outcome of every level are in the course curriculum.
Implementation formats and recommended trajectories
The course fits flexibly into a syllabus — from a year-long elective to an intensive. Detailed estimates are in the course curriculum.
| Format | For whom | Content | Volume | Outcome |
|---|---|---|---|---|
| Introductory module | Colleges, 1st year of university | Parts 1–2 | 16–20 academic hours | The student explains the data path and writes a simple program |
| Full practicum | Engineering classes, IT colleges, 1st year of IT/engineering | All 4 parts, Verilog and FPGA | 30–36 academic hours | Their own 8-bit computer, structural HDL project, FPGA export |
| Year-long elective | School, grades 7–11 | Selected or full trajectory | 34 / 68 academic hours | Logic fundamentals and computer architecture through practice |
| Intensive | Club, Quantorium, summer school, orientation week | Selected module or full course | 5 days × 6 academic hours | Visible project outcome: a circuit, a program, "Snake" or an FPGA project |
How the course fits into educational programmes
The course is a ready-made hands-on module. For schools its alignment can be described through the Federal State Educational Standard (FGOS) and the federal informatics curriculum; for colleges and universities — through the syllabus of a specific discipline. It does not replace an educational programme entirely.
School: FGOS (basic and secondary education)
The course aligns with the informatics topics of the federal working programme and deepens them with practice.
| Topic | Course levels | Observable outcome |
|---|---|---|
| Logic operations, truth tables, logic gates | 2–5 | Builds and checks AND/OR/NOT/XOR circuits, reads a truth table |
| Binary arithmetic, adder | 6–8 | Explains carry and builds an 8-bit adder |
| Flip-flop, register, clocking | 10–12, 15–16 | Explains state storage, the clock edge and counter operation |
| Computer as a programmable device: processor, memory, I/O | 14, 16–18, 21–24 | Builds a training computer, explains the role of PC, RAM, ALU and ports |
| Algorithms, branching, loops, debugging | 23–29, 43 | Writes and debugs a simple assembler program for the training processor |
| Cross-disciplinary skills | 22, 42, 43; crash tests 12, 14, 45 | Formulates a hypothesis, diagnoses an error, fixes the model |
For school implementation the correct positioning is: an elective, an after-school activity or an engineering/IT class module. The course does not replace the core informatics curriculum.
Vocational college
In vocational education the course can be used as a hands-on module within the syllabus of a discipline or an interdisciplinary course. A methodologist maps the course levels to the outcomes of a specific curriculum, qualification and study plan.
| Discipline type | Recommended part | Practical outcome |
|---|---|---|
| Fundamentals of digital electronics / digital circuit design | 1 | Gate circuits, adders, flip-flops, registers |
| Hardware architecture / computer organization | 1–2 | A built training processor, memory, addressing, I/O |
| Low-level programming | 2 | Assembler, loops, branching, memory, peripherals |
| HDL / FPGAs / digital design | 3–4 | Structural Verilog, waveform, RTL, FPGA export |
First year of university
At university the course does not claim to replace the lab cycle of a computer architecture or digital design course. It works well as a common starting practicum and a levelling module, after which a group moves on to ISA, C/assembler, HDL, microcontrollers or real lab benches.
| Teacher's task | Trajectory | Use |
|---|---|---|
| Quickly level the preparation of first-years | 1–12 | Diagnostic entry and self-paced work before the labs start |
| Give a complete model of a computer | 1–18 | Practicum before "Computer Architecture" |
| Link architecture to programming | 19–29 | Lab module on assembler, memory and I/O |
| Introduce digital design | 30–47 | Preparation for Verilog/FPGA labs |
Grading: minimal criteria
The simulator checks solutions automatically, so the share of completed material can be converted into a grade with transparent thresholds. Below is a minimal variant you can put into a working programme today; the full assessment bank is in development.
| Grade | Criterion |
|---|---|
| Pass | At least 60% of levels in the chosen trajectory completed |
| Good (4) | At least 80% of levels in the chosen trajectory completed |
| Excellent (5) | At least 95% of levels in the chosen trajectory completed — or at least 90% with correct concept-check answers |
Hints, failed attempts ("walls") and time are diagnostic indicators: they are not penalized and serve as material for in-class discussion. The teacher adjusts the thresholds in their own working programme.
What a teacher gets right now
Everything needed to get started is already available: the teacher dashboard (Russian-language) and the Library.
- Teacher dashboard — classes, invite codes, student progress and activity, CSV export, printable department report → open (RU)
- Course curriculum — 47 levels, topics, difficulty, estimated time, measurable outcome → open
- Placement diagnostic — 21 items: a well-prepared student starts mid-course, not at the gates → open
- 47 level guides — for lesson prep and solution reviews → open
- Component guides — datasheets for gates, adders, memory, buses, peripherals and processor blocks → open
- Digital logic and Verilog articles (44) — theory for self-study → open
- Assembler guide — instructions of the training processor, formats and examples → open
- First lesson materials — a 90-minute lab scenario and a printable student handout → open (RU)
- Video overview → watch and help → open
- Automatic checking — truth tables, structural and program checkpoints
- AI tutor — offers guiding questions and explanations (availability and quotas may vary)
Technical requirements and limitations of the current version
- Browser and internet: a modern Chrome, Firefox or Edge and internet for the initial page load are required. After loading, the simulation runs in the student's browser.
- No installation required: the course opens via a link and suits ordinary computer classrooms.
- Progress: stored locally in the browser for basic use. Students with school accounts get progress sync across devices; the teacher sees the group's performance. Schematics and chips always stay local in the browser.
- Personal data: no account is needed for basic completion, and progress requires no personal information. When a certificate is issued, the user voluntarily provides their name; details are in the privacy policy.
- Screen-based work: the teacher plans the lesson alternating between in-browser practice, discussing circuits and reflection, in line with the local requirements of the institution.
Roadmap
Already available
- Free basic access with no registration
- RU + EN interface
- School accounts: student class sign-in by invite, teacher dashboard with group progress (Russian-language)
- Group analytics: hints, time, failed attempts; CSV export
- Placement diagnostic: start at the right level
- Automatic checking of circuits and programs
- Certificates for completed parts and the full course, with public verification
- Course curriculum, level guides, component datasheets and articles
In development
- Assignments with deadlines and level access gating
- Class leaderboard and report templates
- Working programme templates, lesson scenarios, a full assessment bank (minimal criteria already available)
- English version of the dashboards
Basic access to the simulator and the library will remain free.
Frequently Asked Questions
Does the course replace a school or university subject?
No. It is a hands-on module on logic fundamentals, digital design and computer architecture. In schools it fits an elective, after-school activity or engineering class; in vocational colleges and universities — a lab practicum, introductory or levelling module within a specific discipline.
Can the course be used in the first year of university?
Yes. Parts 1–2 give a complete model of a processor, memory and programs; parts 3–4 introduce structural Verilog and FPGA. A teacher picks the needed levels: from a short diagnostic module to a full practicum.
What does a lesson require?
A modern browser (Chrome, Firefox or Edge), internet to load the page, and one device per student or pair. No software installation; we recommend testing on a typical device at your institution beforehand. The final FPGA project needs a Tang Nano 9K board, but the board is not required for the main part of the course.
Are student data and progress stored?
Yes. A student joins a class with an invite code and a nickname — no email or password. The teacher sees the group's progress in the dashboard and can export CSV; progress syncs across a student's devices, while schematics and chips stay local in the browser. Classrooms are currently Russian-language; an English dashboard is on the roadmap. Basic use without registration remains available. Which data is processed and how to delete an account — see the school accounts section of the privacy policy.
Can the course be graded?
The simulator automatically checks circuits and programs and includes concept checks. Minimal grading criteria are already published above, in the Grading section: pass — from 60% of levels completed in the chosen trajectory, 'good' — from 80%, 'excellent' — from 95% or from 90% with correct concept-check answers; hints, failed attempts and time are diagnostic, not penalized. The full assessment bank is in development; the teacher sets the grading rules within their own syllabus.
What is issued upon completion?
Certificates of completion for course parts and the full course, with public verification. These are not state-recognized education documents.
How much does it cost?
Basic access is currently free for everyone — schools, colleges and universities — and will remain free for the simulator and the library.
How do I start?
Open the course curriculum, pick a trajectory for your group and launch the first level. For pilot or implementation questions, use the contacts listed on the page.
Run your first lesson as early as this week
Everything is ready to start: the course, guides and solution checking — free, right in the browser.