Help

Basics

Already familiar with logic gates? Take the placement test: 28 questions and 3 hands-on tasks (~10–15 minutes). Based on the result, levels 1 through 30 unlock (without completion marks) — you can start at an advanced level right away. Retakes are allowed: the floor can only go up. Note that the placement test does not mark levels as completed — certificates require real completions.

New to the subject? The circuit design hub explains what the field is, what a circuit is made of, how it differs from programming, and what to read next — a good start before the first level.

For educators and the curious, there is a walkthrough of the course methodology: which pedagogical technique stands behind each mechanic, from the spiral curriculum to formative assessment.

Intros

Before nineteen key levels an interactive intro opens: a short experiment on a mini-circuit ("toggle the switches and notice when the lamp lights up"), the rule put into words, the rule checked on a new circuit, and an example from real hardware. You cannot "fail" an intro: a wrong answer becomes a hint. The intro can be closed at any moment — the game remembers the topic was shown and will not open it again on its own.

If you have taken the placement test and it confirmed you know a topic, its intro is skipped automatically. All topics in plain text (without the interactivity) are collected in the Intros hub:

• NAND — level 2
• The AND gate — level 3
• OR from AND and NOT — level 4
• Composing gates — level 5
• Binary counting — level 6
• Binary addition — level 7
• The bus and the 8-bit word — level 8
• The multiplexer: a track switch for signals — level 9
• Feedback is memory — level 10
• The clock and the D flip-flop — level 11
• The register — level 12
• A command number — level 13
• The ALU and the op code — level 14
• The program counter — level 16
• The decoder — level 17
• Program as data — level 18
• Negative numbers — level 25
• Constants in memory — level 28
• Line concurrency — level 30
• Module instantiation — level 34
• The generate loop — level 37

Signal visualization

Wires on the canvas change color depending on the signal they carry:

• Orange — active bit signal (logic 1)
• Gray — inactive signal (logic 0)
• Blue — active 8-bit bus (value > 0); dark blue — inactive (value 0)

Active wires also show flow dots — small circles moving along the line. They indicate the direction of signal propagation: from a component's output to another's input.

You can toggle input nodes (Input / Bus Input) directly on the canvas without running a test. Click the «0» circle on an input — it switches to «1», the signal instantly propagates through the entire circuit, and all wire colors update. This is great for debugging: manually flip inputs and watch how the circuit responds, without waiting for a full verification.

Error highlighting

When you press ▶ (Run Test), the circuit is checked against the truth table. If any row's expected output doesn't match the actual value:

• The wire leading to a failing output turns red with a bright glow
• The output node itself is highlighted in red with an outer ring

Error highlighting stays until you modify the circuit (add/remove a component or connection) or run the test again. When all tests pass, the highlighting clears automatically.

Element info card

Double-clicking a component on the canvas opens a popover card next to the node: description, category, and truth table. A handy reference: no need to search for documentation — all gate info is right there. Selecting a component in search opens the same card automatically.

The card includes a «Read the article in the library →» link that opens a detailed walkthrough in a new tab. The display is the exception: its double-click cycles the number format (dec/bin/hex). On mobile, the element card opens as the «Info» tab of the bottom panel.

Truth table

A timing diagram is displayed above the truth table. Columns are separated by dashed lines — each clock cycle is distinct.

Hover a row in the table below — the corresponding column highlights on the diagram. Hover a column on the diagram — the corresponding row highlights in the table. This helps match expected and actual values to time intervals. Learn more about timing diagrams →

Test vectors

Each row of the truth table is a test vector: a set of input values and expected output values. When you press ▶ (Run Test), the simulator applies the inputs from the current row, propagates signals through the entire circuit, and compares actual outputs against expected values.

• Combinational levels — all vectors are checked independently: for each row the circuit resets, inputs are applied, outputs are computed. Row order does not matter.
• Sequential levels (with a clock signal) — vectors are applied sequentially, one after another, without resetting state between them. The circuit "remembers" previous steps — just like a real digital circuit with memory. Rows with the special inClock field mark a clock edge: at that moment, flip-flops and registers capture input data.
• Verilog levels — same principles, but checking runs through the Verilog simulator. For sequential designs, the waveform viewer visualizes signal history: inputs, outputs, and internal wires.

A test status appears below the table: green — all vectors passed; red — mismatches found. For failed rows, the "Exp" / "Act" columns show which bits didn't match. Click a failed row to expand a dump of all internal signals — useful for debugging.

Clock

On levels with memory and feedback loops (10–12, 16+), a «Clock» block appears in the right dock. Purely combinational levels (13–15) have no clock — the block hides. In «Sandbox» mode, it is always available. On mobile, the block lives in the task strip drawer.

• ▶ / ⏸ — start / pause automatic clocking. The graph updates at the selected frequency.
• ⏭ — single step: advance exactly one clock tick. Great for debugging — see how state changes after each step.
• Hz — speed slider: from 1 to 100 steps per second. Higher is faster.
• Ticks — tick counter. On the CPU level (16), this is the number of executed instructions.

Step mode (⏭) helps you understand what the circuit does: one click, one tick. Automatic mode (▶) verifies that the circuit runs stably over time.

Controls

• Click an element in the left palette — it appears on the canvas
• Drag an element from the palette — it appears where you drop it
• Drag from an element's port — create a connection
• Delete — remove the selected element
• Mouse wheel — zoom in/out
• [ ] (button next to +/−) — fit the circuit to the canvas
• Ctrl+Z / Ctrl+Shift+Z (Ctrl+Y) — undo/redo circuit changes
• F9 — run circuit verification
• Ctrl+Shift+F — open search for components and theory
• Ctrl+Shift+D — debug report: logs, environment and the current circuit/code (the button to the left of the language switch)

Search components and theory

Press Ctrl+Shift+F (Cmd+Shift+F on Mac) or click the «Search…» field at the top of the left palette to open the command palette — a Spotlight-style search panel.

Start typing a component name, article title, or level — the panel instantly finds matches among:

• Components (datasheets) — NAND, Half Adder, registers, ALU, and more
• Library articles — from «Introduction to Circuit Design» to «Timing Diagrams»
• Level guides — step-by-step walkthroughs for all 67 levels

Navigate with ↑↓ arrows, press Enter to open — a component opens in the popover card, an article or guide opens in a new tab.

Hints

Press the button in the toolbar. The first hint shows a solution guide. The second hint inserts the solution onto the canvas — this step unlocks gradually: open the level guide («Detailed description» in the task strip above the canvas), score 7 failed checks in a row, or spend 10 minutes on the level. Re-taking a completed level is unlocked right away. On some levels, instead of the full solution a scaffold is inserted — a circuit with a few missing wires that you connect yourself; such a scaffold deducts half the penalty.

Modes

• Levels — progress through levels in order with verification
• Sandbox — free experimentation in two variants: "Circuit" (all unlocked elements) and "Verilog" (circuits from code) — see the Sandbox section

Computer map

The «My Computer» menu item opens a map of what you have built: the nine nodes of the machine — inputs and outputs, logic, adder, ALU, memory, clocking, program counter, decoder and processor — and the levels each node grew out of. The «Level N/47» button in the header opens the same map on the «Levels» tab.

• Node states. A block is locked, available, being assembled, learned, part of the computer, or being modernized. The «You are here» and «Next goal» markers show the current level and the nearest step.
• Block card. Clicking a node shows the «What it is» and «Why this block» lines, its levels and guides, the route with the remaining time, a button to the sandbox with a ready recipe, a link to copy the block's URL, and «Show in levels». The «Why» line explains the node's role in the machine and is visible even for a locked block.
• Signal path. The «Show the path» button under the «Why» line highlights the chain of connections the signal travels through the block and labels the order of nodes (for example, «Decoder → ALU → Memory»). Clicking again or pressing Esc turns the highlight off; the card stays open.
• Computer passport. Seven rows: word size, architecture, ROM and RAM size, instruction set, clocking and ports. For a node not built yet, the value reads «Not built yet» along with the level where it appears.
• View mode. The «Base» / «Modernization» switch shows the diagram before and after part 2; your choice is remembered.
• Build replay. The ▶ button next to the switch replays the build step by step: blocks come alive in course order, each block card shows what is already done, and the stage bars grow from zero. Clicking again, pressing Esc or clicking the map stops the replay.

When a level completes a block or moves it to the next stage, the map opens on its own; the first transition (1→2) is the exception — the map starts appearing once the «Logic» block is complete. The «Next →» button at the bottom leads to the following level. The map covers levels 1–29; Verilog and board work stay outside it.

You can save a link to the map: /learn/?computer=logic opens the diagram with the Logic block card, and /learn/?computer=levels opens the «Levels» tab.

Level guides 1–29 in the library lead here too: the «Where it fits in the machine» link opens the level with its block card. The number on the «My Computer» menu item shows how many blocks were completed since the map was last opened.

Sandbox

The Sandbox is a free-building mode: no task, no truth table, no verification (F9 is disabled) — but all base components are available right away: gates, bus operations, registers, the ALU, memory, the display, the gamepad and the random number generator.

• Recipes. An empty canvas shows a welcome overlay with six ready-made circuits: "Clock Beacon", "Half Adder", "0–255 Counter", "Random Number Generator", "Running Light" and "Processor with Assembly". Clicking a card builds the circuit instantly — a convenient starting point for experiments. The "Processor with Assembly" recipe also opens via the link /en/learn/?mode=sandbox&recipe=asm_cpu.
• Clocking. The «Clock» block in the right dock is always available: ▶ — continuous clock, ⏭ — single tick, the slider sets the speed from 1 to 100 Hz. Registers, DFF, the program counter and the RNG change state on the clock edge.
• "Assembler" tab. Appears automatically when a ROM is on the canvas. Programs use the byte format: one instruction — one byte ([7:4] opcode, [3:0] operand). The "Run" button compiles the text into ROM memory and starts the clock. Build a minimal computer from a ROM, a program counter and registers — or load the "Running Light" recipe and rewrite its program. More about the assembler →
• Display. Double-clicking a display cycles the number format: decimal, binary or hexadecimal.
• Saving. The circuit autosaves in the browser and is restored the next time you enter the mode. The 🗑 "Clear canvas" button removes everything and shows the recipe cards again.
• AI Tutor. In the sandbox the tutor works as usual: explains components, suggests experiment ideas and answers questions about the mode's capabilities and the assembler.

The "Verilog" variant. There is no separate sandbox button anymore: the sandbox lives in the single top-bar menu as two items — «Sandbox·Circuit» and «Sandbox·Verilog». Switching preserves the state of both modes. The Verilog variant offers the same freedom, but the circuit is described in code: the Verilog editor on the left, the RTL Viewer building a schematic from the code on the right.

• Language. Structural Verilog is supported: module, input/output/wire (including buses), the and/or/not/xor/nand/nor primitives, dff (q, d, clk) and generate-for. Behavioral constructs (always, if, case, reg, assign) are not supported. The clock input is named clk, and all dffs are clocked from it.
• Recipes. An empty sandbox offers five ready-made examples: "Half Adder", "Blink (T flip-flop)", "4-bit Counter", "MUX 2→1", "Running Light". Clicking a card inserts the code into the editor.
• Running. Buttons ⏭ (one tick), ▶ (continuous) and ⟲ (reset); F9 also steps once. Results appear as a waveform: inputs, outputs and internal signals after each tick.
• "Inputs" panel. Every input port of the top module (except clk) gets a control: a toggle for 1-bit inputs, a hex stepper for buses. Values are applied to the circuit before each tick.
• Saving. The project autosaves and is kept separately from the circuit sandbox. The 🗑 button restores the empty project and shows the recipe cards again.
• AI Tutor. Knows the mode's capabilities: explains primitives and dff, helps read the waveform and suggests structural techniques.

Verilog Editor and Debugging

On Verilog levels (30–47) and in the "Verilog" sandbox, the editor helps you find mistakes before running the tests, and the results show exactly where the circuit diverges from the expectation.

• Readable diagnostics. Parser errors, warnings and simulator messages state the signal name, the line and what was expected. An unexpected token is described in words: «name», «number», «symbol», «keyword».
• Click an error to jump to the line. Every entry in the error panel is clickable: the editor places the cursor on the reported line and scrolls it to the center of the screen. In multi-file projects the jump lands in the file the error belongs to.
• Warnings while typing. Unused and undriven wires (declared but not connected) are flagged as warnings as you edit — before any test runs. Warnings do not block checking.
• Autocompletion. After the first letters, the editor offers the module's port and wire names. For a bus it lists indexed variants: bus[0]…bus[7]. Completion also works inside the index bracket — type bus[ and pick a bit. In a multi-file project the project's own modules are offered with their full port lists.
• Snippets. A module skeleton, a generate for block and a dff bank are inserted from the completion list; Tab accepts the insertion.
• Primitive hints. Hover over a primitive name (and, dff and others) to see its port order. Hints also work for the built-in RAM256/ROM modules and for multi-file project modules: inputs are separated from outputs by an arrow. The current line is highlighted so you don't lose your place in the code.
• Brackets. An opening bracket closes automatically and matching brackets are highlighted — nested port lists are easier to type without mistakes.
• Bit-level bus comparison. In the results table, mismatched bus bits are highlighted individually: you can see which bits are correct without comparing binary strings by eye.
• Error panel summary. Above the list a short tally is shown: "Errors: N · Warnings: M".
• Wire dump. A table row with internal signals is marked with a pointer cursor: clicking it expands the values of every wire in the circuit. The BIN/HEX toggle in the table heading switches the number system for the table and all open dumps at once; matching buses are shown in HEX, mismatched ones stay binary with per-bit highlighting.
• File tab badges. In a multi-file project each file tab carries a counter: red for errors, amber for warnings — visible even when the file is not open.
• ROM editor. On memory levels the editor accepts lines with inline comments (0x05 // start), and the "Level program" button restores the factory program in one click.
• First failure marker. On sequential circuits (with clk), the waveform marks the column and tick number where an output first diverged from the expectation — the state before that tick can be considered correct.
• Collapsing the table. A button on the results panel collapses the truth table, freeing space for code and the waveform.

A detailed walkthrough of the debugging environment is in the article "Debugging Verilog Circuits".

AI Tutor

A 💬 bubble in the bottom-right corner of the canvas opens the AI Tutor panel, which analyzes your circuit, finds errors, and asks guiding questions in a Socratic style. You can drag the panel by its header to a convenient spot (double-clicking the header returns it to its original place). 20 requests per day are available.

Shortcut buttons send common requests:

• Check circuit — find errors without giving a solution
• Explain level — rephrase the task in simple terms
• Explain from scratch — walk through the topic from the very basics
• I give up — show a step-by-step solution

AI Tutor can make mistakes. Do not blindly trust it — double-check results.

Game Economy

Completing levels successfully earns you the in-game currency — Transistors (T). The currency serves as a scoring system and is not spent on anything.

• Level reward depends on difficulty: easy levels (1–5) give +50 T, medium (6–11) — +100 T, hard (12–29) — +150 T.
• Hint penalty: using the ready-made solution (2nd hint) deducts an amount equal to the reward, with a minus sign (e.g., −50 T). Your balance can go negative.
• Scaffold instead of solution: on some levels the second step inserts a circuit with gaps that you close yourself and deducts half the penalty (e.g., −25 T instead of −50 T). Complete the wiring and it is your own result.
• Re-grade: if you passed a level with a penalty, then reset it and built the circuit on your own — the penalty is refunded, and the full reward is granted. The system rewards learning!

Your current transistor balance is visible in the «Profile · N T» menu item and in the Engineer Profile itself — a table with your full completion history: which levels are done, when, how many hints used, and how many transistors earned. The «Level N/47» button in the header opens «My Computer» on the «Levels» tab.

Transistor Run

Besides the circuit simulator, the project includes the game «Transistor Run» — a game sub-level of the practicum that unlocks after the introductory levels. In platformer form you route the path for the signal, assembling gates from transistors, and from gates — adders, flip-flops and registers. The levels carry plaques of the "Museum on the Board": pressing E opens a short story about a brand or machine from computing history. The game reinforces what you've learned and boosts engagement before working on the simulator canvas.

The full description of the game — rules, mechanics, and how it ties into the course levels — is on the "Transistor Run: about the game" page.

Accounts and Classes

For schools and universities the game offers optional accounts. Basic access remains free and registration-free — an account is only needed for progress sync and class studies.

• Student login: via a personal login code (STU-XXXXX-XXXXX) — no email or password. First time in a class: via the class code (ERSH-XXXX-XXXX) from the teacher and a nickname on the Student Cabinet page (in Russian) or via the "Log in" button in the Engineer Profile.
• Personal login code: at registration (or when accounts are handed out by the teacher) the site shows a personal code like STU-XXXXX-XXXXX — save it. It replaces both the class code and the nickname: it is the only thing needed. The code is shown once; if lost, ask the teacher to reissue it — progress is kept.
• Sync: progress (completed levels, hints, time) is merged across devices. Circuits and chips are stored locally in the browser and are not synced.
• Student cabinet: class, teacher, progress by parts and levels, nickname change, leaving the class and deleting the account.
• Teacher cabinet: classes, bulk creation of student accounts (list or nickname generator), printable sheet of login codes, student progress and activity, CSV export — /teacher.html (in Russian; access by request via the schools and universities page). For lesson preparation — teaching cards with lesson plans and common mistakes.
• Can a teacher create accounts for students? Yes: in the class drill-down there is a "Student accounts" section — enter nicknames one by one (real names are allowed) or generate a "prefix + number" series. Login codes STU-… are shown once: print the sheet (cut-out cards) or copy the CSV. If a student loses the code — reissue it via the "Code" button on the student or "Reissue codes" on the class; active sessions are not interrupted.
• Teacher assignments: on the "Assignments" tab of the teacher cabinet you can create your own assignment: a goal, a truth table (up to 3 inputs and 2 outputs) and allowed gates. The editor is a four-step timeline («Start» → «Text» → «Structure» → «Check») with completion ticks; the source is your own assignment or one of 15 templates in four difficulty tiers (a template keeps the text already entered). Students see it in the "Assignments" item of the top menu (with a badge of unsolved ones) — the list opens as a modal, an active assignment plays like a level. Results (solved, gates, delay, attempts, hint opens) reach the teacher in the assignment results and in analytics. Up to 20 active assignments per class; after the first results only the texts can be edited. In assignment mode the AI tutor is disabled — the test is solved on your own.
• Privacy: consent is given by the student (14+), a real name is optional and visible only to the teacher. Details — in the "School and university accounts" section of the privacy policy.

Library

Detailed materials are available in the Library:

• Level Guides — step-by-step solutions for all 67 levels
• Assembler Manual — complete instruction set documentation
• Circuitry Articles — logic gates and fundamentals

Course part overviews — the arc of each part, its main ideas and what you build by the end: part 1, part 2, part 3, part 4.

An AI tutor is available on library pages: highlight any passage and click "Ask a question" — the tutor will explain it in the context of the article. Or open the chat with the floating button at the right edge and ask anything. The daily request limit is shared with the game — 20 per day.

Tools

Besides the game there are standalone browser tools that help when working with truth tables:

• Truth Table Generator — a full table for a Boolean formula
• Boolean Function Calculator — PDNF, PCNF, the Zhegalkin polynomial, Post classes, minimization and a Karnaugh map with step-by-step solutions
• Logic Circuit Simulator — a standalone page with a canvas for free experiments