Concurrency: Code Is a Blueprint

The thirtieth intro opens part three of the course: hardware design in Verilog. Step one is realising that a line of code here is not an order but the description of a part on a blueprint.

Experiment: one circuit, two gates

The circuit has two gates: NOT flips bit A, AND combines the result with B. Walking through all four combinations gives one answer: the Out lamp is lit only when A=0 and B=1. One circuit, one behaviour.

Predict: two lines of a module

A module has two lines: and step1 (w, a, b); and or step2 (out, w, c);. With a=1, b=1, c=0 the output out is 1: both parts work at the same time, w becomes a one, and the OR immediately yields the result. The lines never "catch up" with each other.

The rule: a blueprint, not a to-do list

A line of Verilog describes a part of the blueprint, like an element on a sheet: a blueprint has no "before" or "after". This property is called concurrency. In and my_gate (out, a, b); the part type (and) comes first, then its name (my_gate), and inside the parentheses the output goes first — where the result goes.

Where it is used

On this level you write your first line of Verilog and call an AND gate. Every level of part three adds new parts to the blueprint — and none of them waits in a queue, exactly like in a real chip.